From nobody Mon Feb 9 10:48:40 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500415863971108.91894551955829; Tue, 18 Jul 2017 15:11:03 -0700 (PDT) Received: from localhost ([::1]:58832 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXahp-0006uz-Ei for importer@patchew.org; Tue, 18 Jul 2017 18:11:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48733) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXaPo-0005nB-9s for qemu-devel@nongnu.org; Tue, 18 Jul 2017 17:52:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dXaPm-00043f-V3 for qemu-devel@nongnu.org; Tue, 18 Jul 2017 17:52:24 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:48448) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dXaOY-0003V2-2e for qemu-devel@nongnu.org; Tue, 18 Jul 2017 17:52:22 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1dXaOS-0000K5-TA; Tue, 18 Jul 2017 23:51:01 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1dXaOO-00011J-Im; Tue, 18 Jul 2017 23:50:56 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Tue, 18 Jul 2017 23:50:22 +0200 Message-Id: <20170718215050.3812-4-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170718215050.3812-1-aurelien@aurel32.net> References: <20170718215050.3812-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PULL 03/31] target/sh4: fix FPSCR cause vs flag inversion X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The floating-point status/control register contains cause and flag bits. The cause bits are set to 0 before executing the instruction, while the flag bits hold the status of the exception generated after the field was last cleared. Message-Id: <20170702202814.27793-4-aurelien@aurel32.net> Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target/sh4/op_helper.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index f228daf125..f2e39c5ca6 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -219,29 +219,29 @@ static void update_fpscr(CPUSH4State *env, uintptr_t = retaddr) =20 xcpt =3D get_float_exception_flags(&env->fp_status); =20 - /* Clear the flag entries */ - env->fpscr &=3D ~FPSCR_FLAG_MASK; + /* Clear the cause entries */ + env->fpscr &=3D ~FPSCR_CAUSE_MASK; =20 if (unlikely(xcpt)) { if (xcpt & float_flag_invalid) { - env->fpscr |=3D FPSCR_FLAG_V; + env->fpscr |=3D FPSCR_CAUSE_V; } if (xcpt & float_flag_divbyzero) { - env->fpscr |=3D FPSCR_FLAG_Z; + env->fpscr |=3D FPSCR_CAUSE_Z; } if (xcpt & float_flag_overflow) { - env->fpscr |=3D FPSCR_FLAG_O; + env->fpscr |=3D FPSCR_CAUSE_O; } if (xcpt & float_flag_underflow) { - env->fpscr |=3D FPSCR_FLAG_U; + env->fpscr |=3D FPSCR_CAUSE_U; } if (xcpt & float_flag_inexact) { - env->fpscr |=3D FPSCR_FLAG_I; + env->fpscr |=3D FPSCR_CAUSE_I; } =20 - /* Accumulate in cause entries */ - env->fpscr |=3D (env->fpscr & FPSCR_FLAG_MASK) - << (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT); + /* Accumulate in flag entries */ + env->fpscr |=3D (env->fpscr & FPSCR_CAUSE_MASK) + >> (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT); =20 /* Generate an exception if enabled */ cause =3D (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT; --=20 2.11.0