From nobody Mon Feb 9 08:58:03 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500415442274524.2593796208646; Tue, 18 Jul 2017 15:04:02 -0700 (PDT) Received: from localhost ([::1]:58798 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXaaz-00004s-2e for importer@patchew.org; Tue, 18 Jul 2017 18:03:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48608) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXaPl-0005jd-F2 for qemu-devel@nongnu.org; Tue, 18 Jul 2017 17:52:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dXaPk-000400-CN for qemu-devel@nongnu.org; Tue, 18 Jul 2017 17:52:21 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:48478) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dXaOY-0003V8-3f for qemu-devel@nongnu.org; Tue, 18 Jul 2017 17:52:20 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1dXaOS-0000KL-Bm; Tue, 18 Jul 2017 23:51:00 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1dXaOP-00012t-RU; Tue, 18 Jul 2017 23:50:57 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Tue, 18 Jul 2017 23:50:36 +0200 Message-Id: <20170718215050.3812-18-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170718215050.3812-1-aurelien@aurel32.net> References: <20170718215050.3812-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PULL 17/31] target/sh4: Hoist fp register bank selection X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Compute which register bank to use once at the start of translation. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson Message-Id: <20170718200255.31647-14-rth@twiddle.net> Signed-off-by: Aurelien Jarno --- target/sh4/translate.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index b706a6a153..bc6f33970b 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -42,6 +42,7 @@ typedef struct DisasContext { int bstate; int memidx; int gbank; + int fbank; uint32_t delayed_pc; int singlestep_enabled; uint32_t features; @@ -353,12 +354,12 @@ static inline void gen_store_fpr64(DisasContext *ctx,= TCGv_i64 t, int reg) =20 #define REG(x) cpu_gregs[(x) ^ ctx->gbank] #define ALTREG(x) cpu_gregs[(x) ^ ctx->gbank ^ 0x10] +#define FREG(x) cpu_fregs[(x) ^ ctx->fbank] =20 -#define FREG(x) cpu_fregs[ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)] #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) -#define XREG(x) FREG(XHACK(x)) +#define XREG(x) FREG(XHACK(x)) /* Assumes lsb of (x) is always 0 */ -#define DREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)) +#define DREG(x) ((x) ^ ctx->fbank) =20 #define CHECK_NOT_DELAY_SLOT \ if (ctx->envflags & DELAY_SLOT_MASK) { \ @@ -2232,6 +2233,7 @@ void gen_intermediate_code(CPUSH4State * env, struct = TranslationBlock *tb) ctx.has_movcal =3D (ctx.tbflags & TB_FLAG_PENDING_MOVCA); ctx.gbank =3D ((ctx.tbflags & (1 << SR_MD)) && (ctx.tbflags & (1 << SR_RB))) * 0x10; + ctx.fbank =3D ctx.tbflags & FPSCR_FR ? 0x10 : 0; =20 max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { --=20 2.11.0