From nobody Mon Feb 9 14:33:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500408336065779.016577112727; Tue, 18 Jul 2017 13:05:36 -0700 (PDT) Received: from localhost ([::1]:58354 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXYkP-0007ZO-Dg for importer@patchew.org; Tue, 18 Jul 2017 16:05:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49513) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXYic-000631-LN for qemu-devel@nongnu.org; Tue, 18 Jul 2017 16:03:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dXYiY-0004Ot-I6 for qemu-devel@nongnu.org; Tue, 18 Jul 2017 16:03:42 -0400 Received: from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:34537) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dXYiY-0004ON-CN for qemu-devel@nongnu.org; Tue, 18 Jul 2017 16:03:38 -0400 Received: by mail-qk0-x243.google.com with SMTP id q66so3779211qki.1 for ; Tue, 18 Jul 2017 13:03:38 -0700 (PDT) Received: from bigtime.com ([101.165.234.197]) by smtp.gmail.com with ESMTPSA id b201sm2339817qkg.5.2017.07.18.13.03.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Jul 2017 13:03:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=zNc2nv4j05eDeV4SdC5HCZecmBsYHkb5apuW+dZ9vcA=; b=S8PmYbeDf09FzsVxiEQvEZ6MHxW6Gka2Ig6x9UXpU+R9PnHeUJbOciOkiV/wz318Mp ldpT/eXfQ0j++GkmFUxmrfFXK53VBx7Mhf8HTokxEHJxUgKY+axht/yOK9mgZO6LFmjC t7qEy0pCg2j2MUQEuT8bAtBrD4EP6CBe1coFLdpITFTu2n4uST+UEITo5u+Y8WEr6F9x QM9HOi/gokkkxv9Lq3+eiXA2ztxrUFLqpitKm+kC1Nhsi9lF9EFW/+nJ25xw2wU8pLGR ZndWSBwm3ugBWWXAbr6pZ4AzFxGEtskeCmJxNw524dd4HL3vpQc7+vuIC2K7EBXJX05B N3gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=zNc2nv4j05eDeV4SdC5HCZecmBsYHkb5apuW+dZ9vcA=; b=pWn/wumYN6jTbPfaJ9f1VrQmMEb8sj8xLLiPcZIvAOdk30Exk78wFJz5fKSDhXgFOt iaIZqPOAQLV1gtNaSIgR1G0s+dydJ+JN5IVFb+WYdeC9bS3pK+kXHQqcRUOgvBBPtS9i RnWhJGoCBiMatCbEE7S/ZjCmK/bVt2CbZVJUBHIhXBgo3jhZ4fOyV5Q5Ah8Yi8CqrqN7 yooTSCohMUwxhDlL/TWfnm3axsgU4l3vcweHMIUkHXP6k1zOYFXCpCg1vpfDelc+WBes Y3TF8tq99p3ufdloLCvMbwQMQMlWTdr5MBc1w2wonnonu8sjyFsu8QFe3iBpaDyL7wQV C7WA== X-Gm-Message-State: AIVw110aB/NM36s97F/aIHobdG9y8FqovHTmzdkW/fREfKrlECJmhT/y 0DcMXk/4ybObUNN37Qk= X-Received: by 10.55.164.209 with SMTP id n200mr4095028qke.159.1500408217382; Tue, 18 Jul 2017 13:03:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 18 Jul 2017 10:02:26 -1000 Message-Id: <20170718200255.31647-2-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170718200255.31647-1-rth@twiddle.net> References: <20170718200255.31647-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH v3 01/30] target/sh4: Use cmpxchg for movco X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" As for other targets, cmpxchg isn't quite right for ll/sc, suffering from an ABA race, but is sufficient to implement portable atomic operations. Signed-off-by: Richard Henderson --- V2: Clear lock_addr in rte, do_interrupt, syscall entry, & signal delivery. Fix movli to tollerate overlap between R0 and REG(B11_8). --- target/sh4/cpu.h | 3 ++- linux-user/main.c | 1 + linux-user/signal.c | 2 ++ target/sh4/helper.c | 2 +- target/sh4/translate.c | 72 +++++++++++++++++++++++++++++-----------------= ---- 5 files changed, 48 insertions(+), 32 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index ffb9168..b15116e 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -169,7 +169,8 @@ typedef struct CPUSH4State { tlb_t itlb[ITLB_SIZE]; /* instruction translation table */ tlb_t utlb[UTLB_SIZE]; /* unified translation table */ =20 - uint32_t ldst; + uint32_t lock_addr; + uint32_t lock_value; =20 /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; diff --git a/linux-user/main.c b/linux-user/main.c index ad03c9e..30f0ae1 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -2673,6 +2673,7 @@ void cpu_loop(CPUSH4State *env) switch (trapnr) { case 0x160: env->pc +=3D 2; + env->lock_addr =3D -1; ret =3D do_syscall(env, env->gregs[3], env->gregs[4], diff --git a/linux-user/signal.c b/linux-user/signal.c index 3d18d1b..ddfd75c 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -3566,6 +3566,7 @@ static void setup_frame(int sig, struct target_sigact= ion *ka, regs->gregs[5] =3D 0; regs->gregs[6] =3D frame_addr +=3D offsetof(typeof(*frame), sc); regs->pc =3D (unsigned long) ka->_sa_handler; + regs->lock_addr =3D -1; =20 unlock_user_struct(frame, frame_addr, 1); return; @@ -3626,6 +3627,7 @@ static void setup_rt_frame(int sig, struct target_sig= action *ka, regs->gregs[5] =3D frame_addr + offsetof(typeof(*frame), info); regs->gregs[6] =3D frame_addr + offsetof(typeof(*frame), uc); regs->pc =3D (unsigned long) ka->_sa_handler; + regs->lock_addr =3D -1; =20 unlock_user_struct(frame, frame_addr, 1); return; diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 28d93c2..df7c000 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -87,7 +87,6 @@ void superh_cpu_do_interrupt(CPUState *cs) int do_exp, irq_vector =3D cs->exception_index; =20 /* prioritize exceptions over interrupts */ - do_exp =3D cs->exception_index !=3D -1; do_irq =3D do_irq && (cs->exception_index =3D=3D -1); =20 @@ -171,6 +170,7 @@ void superh_cpu_do_interrupt(CPUState *cs) env->spc =3D env->pc; env->sgr =3D env->gregs[15]; env->sr |=3D (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB); + env->lock_addr =3D -1; =20 if (env->flags & DELAY_SLOT_MASK) { /* Branch instruction should be executed again before delay slot. = */ diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 4c3512f..45f7661 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -68,7 +68,8 @@ static TCGv cpu_gregs[24]; static TCGv cpu_sr, cpu_sr_m, cpu_sr_q, cpu_sr_t; static TCGv cpu_pc, cpu_ssr, cpu_spc, cpu_gbr; static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl; -static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_ldst; +static TCGv cpu_pr, cpu_fpscr, cpu_fpul; +static TCGv cpu_lock_addr, cpu_lock_value; static TCGv cpu_fregs[32]; =20 /* internal register indexes */ @@ -151,8 +152,12 @@ void sh4_translate_init(void) offsetof(CPUSH4State, delayed_cond), "_delayed_cond_"); - cpu_ldst =3D tcg_global_mem_new_i32(cpu_env, - offsetof(CPUSH4State, ldst), "_ldst_"); + cpu_lock_addr =3D tcg_global_mem_new_i32(cpu_env, + offsetof(CPUSH4State, lock_addr), + "_lock_addr_"); + cpu_lock_value =3D tcg_global_mem_new_i32(cpu_env, + offsetof(CPUSH4State, lock_value), + "_lock_value_"); =20 for (i =3D 0; i < 32; i++) cpu_fregs[i] =3D tcg_global_mem_new_i32(cpu_env, @@ -430,6 +435,7 @@ static void _decode_opc(DisasContext * ctx) CHECK_NOT_DELAY_SLOT gen_write_sr(cpu_ssr); tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc); + tcg_gen_movi_i32(cpu_lock_addr, -1); ctx->envflags |=3D DELAY_SLOT_RTE; ctx->delayed_pc =3D (uint32_t) - 1; ctx->bstate =3D BS_STOP; @@ -1527,35 +1533,41 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_mov_i32(REG(B11_8), cpu_sr_t); return; case 0x0073: - /* MOVCO.L - LDST -> T - If (T =3D=3D 1) R0 -> (Rn) - 0 -> LDST - */ + /* MOVCO.L: if (lock still held) R0 -> (Rn), T=3D1; else T=3D0. + Approximate "lock still held" with a comparison of address + from the MOVLI insn and a cmpxchg with the value read. */ if (ctx->features & SH_FEATURE_SH4A) { - TCGLabel *label =3D gen_new_label(); - tcg_gen_mov_i32(cpu_sr_t, cpu_ldst); - tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label); - tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL); - gen_set_label(label); - tcg_gen_movi_i32(cpu_ldst, 0); - return; - } else - break; + TCGLabel *fail =3D gen_new_label(); + TCGLabel *done =3D gen_new_label(); + + tcg_gen_brcond_i32(TCG_COND_NE, REG(B11_8), cpu_lock_addr, fai= l); + + tcg_gen_atomic_cmpxchg_i32(cpu_sr_t, REG(B11_8), cpu_lock_valu= e, + REG(0), ctx->memidx, MO_TEUL); + tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_t, + cpu_sr_t, cpu_lock_value); + tcg_gen_br(done); + + gen_set_label(fail); + tcg_gen_movi_i32(cpu_sr_t, 0); + + gen_set_label(done); + tcg_gen_movi_i32(cpu_lock_addr, -1); + return; + } else { + break; + } case 0x0063: - /* MOVLI.L @Rm,R0 - 1 -> LDST - (Rm) -> R0 - When interrupt/exception - occurred 0 -> LDST - */ - if (ctx->features & SH_FEATURE_SH4A) { - tcg_gen_movi_i32(cpu_ldst, 0); - tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL); - tcg_gen_movi_i32(cpu_ldst, 1); - return; - } else - break; + /* MOVLI.L @Rm -> R0, and remember the address and value loaded. = */ + if (ctx->features & SH_FEATURE_SH4A) { + tcg_gen_qemu_ld_i32(cpu_lock_value, REG(B11_8), + ctx->memidx, MO_TESL); + tcg_gen_mov_i32(cpu_lock_addr, REG(B11_8)); + tcg_gen_mov_i32(REG(0), cpu_lock_value); + return; + } else { + break; + } case 0x0093: /* ocbi @Rn */ { gen_helper_ocbi(cpu_env, REG(B11_8)); --=20 2.9.4