From nobody Tue Feb 10 21:41:07 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150039448062453.81268346778711; Tue, 18 Jul 2017 09:14:40 -0700 (PDT) Received: from localhost ([::1]:57580 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXV8u-0005iR-9x for importer@patchew.org; Tue, 18 Jul 2017 12:14:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45331) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXV76-0004NQ-NF for qemu-devel@nongnu.org; Tue, 18 Jul 2017 12:12:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dXV75-0001vJ-7D for qemu-devel@nongnu.org; Tue, 18 Jul 2017 12:12:44 -0400 Received: from mx1.redhat.com ([209.132.183.28]:40270) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dXV74-0001uo-Tf for qemu-devel@nongnu.org; Tue, 18 Jul 2017 12:12:43 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id EE331285B9; Tue, 18 Jul 2017 16:12:41 +0000 (UTC) Received: from probe.bos.redhat.com (dhcp-17-231.bos.redhat.com [10.18.17.231]) by smtp.corp.redhat.com (Postfix) with ESMTP id 4652E7A24B; Tue, 18 Jul 2017 16:12:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com EE331285B9 Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=jsnow@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com EE331285B9 From: John Snow To: qemu-devel@nongnu.org Date: Tue, 18 Jul 2017 12:12:28 -0400 Message-Id: <20170718161230.21917-3-jsnow@redhat.com> In-Reply-To: <20170718161230.21917-1-jsnow@redhat.com> References: <20170718161230.21917-1-jsnow@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Tue, 18 Jul 2017 16:12:42 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 2/4] ahci: Isolate public AHCI interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, jsnow@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Begin separating the public/private interface by removing the minimum set of information used by code outside of hw/ide/ and calling this a new ahci_public.h file, which will be renamed to ahci.h in a future patch. Signed-off-by: John Snow Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20170623220926.11479-3-jsnow@redhat.com Signed-off-by: John Snow --- include/hw/ide/ahci.h | 57 +++------------------------ include/hw/ide/ahci_public.h | 91 ++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 96 insertions(+), 52 deletions(-) create mode 100644 include/hw/ide/ahci_public.h diff --git a/include/hw/ide/ahci.h b/include/hw/ide/ahci.h index f866bbf..70a0140 100644 --- a/include/hw/ide/ahci.h +++ b/include/hw/ide/ahci.h @@ -21,9 +21,10 @@ * */ =20 -#ifndef HW_IDE_AHCI_H -#define HW_IDE_AHCI_H +#ifndef HW_IDE_AHCI_INTERNAL_H +#define HW_IDE_AHCI_INTERNAL_H =20 +#include "hw/ide/ahci_public.h" #include "hw/sysbus.h" =20 #define AHCI_MEM_BAR_SIZE 0x1000 @@ -210,14 +211,6 @@ #define SATA_CAP_REV 0x2 #define SATA_CAP_BAR 0x4 =20 -typedef struct AHCIControlRegs { - uint32_t cap; - uint32_t ghc; - uint32_t irqstatus; - uint32_t impl; - uint32_t version; -} AHCIControlRegs; - typedef struct AHCIPortRegs { uint32_t lst_addr; uint32_t lst_addr_hi; @@ -251,8 +244,6 @@ typedef struct AHCI_SG { uint32_t flags_size; } QEMU_PACKED AHCI_SG; =20 -typedef struct AHCIDevice AHCIDevice; - typedef struct NCQTransferState { AHCIDevice *drive; BlockAIOCB *aiocb; @@ -286,27 +277,13 @@ struct AHCIDevice { NCQTransferState ncq_tfs[AHCI_MAX_CMDS]; }; =20 -typedef struct AHCIState { - DeviceState *container; - - AHCIDevice *dev; - AHCIControlRegs control_regs; - MemoryRegion mem; - MemoryRegion idp; /* Index-Data Pair I/O port space */ - unsigned idp_offset; /* Offset of index in I/O port space */ - uint32_t idp_index; /* Current IDP index */ - int32_t ports; - qemu_irq irq; - AddressSpace *as; -} AHCIState; - -typedef struct AHCIPCIState { +struct AHCIPCIState { /*< private >*/ PCIDevice parent_obj; /*< public >*/ =20 AHCIState ahci; -} AHCIPCIState; +}; =20 #define TYPE_ICH9_AHCI "ich9-ahci" =20 @@ -372,35 +349,11 @@ void ahci_uninit(AHCIState *s); =20 void ahci_reset(AHCIState *s); =20 -int32_t ahci_get_num_ports(PCIDevice *dev); -void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd); - #define TYPE_SYSBUS_AHCI "sysbus-ahci" #define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_= AHCI) =20 -typedef struct SysbusAHCIState { - /*< private >*/ - SysBusDevice parent_obj; - /*< public >*/ - - AHCIState ahci; - uint32_t num_ports; -} SysbusAHCIState; - #define TYPE_ALLWINNER_AHCI "allwinner-ahci" #define ALLWINNER_AHCI(obj) OBJECT_CHECK(AllwinnerAHCIState, (obj), \ TYPE_ALLWINNER_AHCI) =20 -#define ALLWINNER_AHCI_MMIO_OFF 0x80 -#define ALLWINNER_AHCI_MMIO_SIZE 0x80 - -struct AllwinnerAHCIState { - /*< private >*/ - SysbusAHCIState parent_obj; - /*< public >*/ - - MemoryRegion mmio; - uint32_t regs[ALLWINNER_AHCI_MMIO_SIZE/4]; -}; - #endif /* HW_IDE_AHCI_H */ diff --git a/include/hw/ide/ahci_public.h b/include/hw/ide/ahci_public.h new file mode 100644 index 0000000..5a06537 --- /dev/null +++ b/include/hw/ide/ahci_public.h @@ -0,0 +1,91 @@ +/* + * QEMU AHCI Emulation + * + * Copyright (c) 2010 qiaochong@loongson.cn + * Copyright (c) 2010 Roland Elek + * Copyright (c) 2010 Sebastian Herbszt + * Copyright (c) 2010 Alexander Graf + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + */ + +#ifndef HW_IDE_AHCI_H +#define HW_IDE_AHCI_H + +#include "hw/sysbus.h" + +typedef struct AHCIDevice AHCIDevice; + +typedef struct AHCIControlRegs { + uint32_t cap; + uint32_t ghc; + uint32_t irqstatus; + uint32_t impl; + uint32_t version; +} AHCIControlRegs; + +typedef struct AHCIState { + DeviceState *container; + + AHCIDevice *dev; + AHCIControlRegs control_regs; + MemoryRegion mem; + MemoryRegion idp; /* Index-Data Pair I/O port space */ + unsigned idp_offset; /* Offset of index in I/O port space */ + uint32_t idp_index; /* Current IDP index */ + int32_t ports; + qemu_irq irq; + AddressSpace *as; +} AHCIState; + +typedef struct AHCIPCIState AHCIPCIState; + +#define TYPE_ICH9_AHCI "ich9-ahci" + +#define ICH_AHCI(obj) \ + OBJECT_CHECK(AHCIPCIState, (obj), TYPE_ICH9_AHCI) + +int32_t ahci_get_num_ports(PCIDevice *dev); +void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd); + +#define TYPE_SYSBUS_AHCI "sysbus-ahci" +#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_= AHCI) + +typedef struct SysbusAHCIState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + AHCIState ahci; + uint32_t num_ports; +} SysbusAHCIState; + +#define TYPE_ALLWINNER_AHCI "allwinner-ahci" +#define ALLWINNER_AHCI(obj) OBJECT_CHECK(AllwinnerAHCIState, (obj), \ + TYPE_ALLWINNER_AHCI) + +#define ALLWINNER_AHCI_MMIO_OFF 0x80 +#define ALLWINNER_AHCI_MMIO_SIZE 0x80 + +struct AllwinnerAHCIState { + /*< private >*/ + SysbusAHCIState parent_obj; + /*< public >*/ + + MemoryRegion mmio; + uint32_t regs[ALLWINNER_AHCI_MMIO_SIZE/4]; +}; + +#endif /* HW_IDE_AHCI_H */ --=20 2.9.4