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[173.197.98.123]) by smtp.gmail.com with ESMTPSA id w66sm27366075pfi.63.2017.07.15.10.30.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 10:30:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=xpR65Hr+R1NXSP/10kPJD7y4FpYL20qxmLdeA3J1WMk=; b=J3uhkgdSSvCmhIQhKL0qMk/TFu43azQDkkuJ+nonVLsaVXTUQWevK9QlfBaqxErto1 FJyL5VLeTqTERWEViI0qzsJjD8CQZJK3AXc2xeFNkw0bPksVuL7BNMI0kHsnCZ9KWpuz q15Z8I1wdbeZkb9FLs4Xh41aHJjikhpmXBepI+IDr+5t8lO393qdPTBFBGfH9ElJ0WfW 1ecemKFPFR3dpaF0ryERv90c0guPTptbdounQ9rURIasDlnPG3kRLUawzFP+ZNNpvuSK Rq0OkbgdxjwBhbChqds9VOpSX06gqAzwiTJ93ibOVDbeb7vULo6JBvXmcSgILkpJkECQ KkSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=xpR65Hr+R1NXSP/10kPJD7y4FpYL20qxmLdeA3J1WMk=; b=iO1zkVelWd6Jvqdln1lD5JN9qXMItVTlMe5zVf1hwVj+z6hGm5tY0WmleVH60WpV7m 7QESpNJxXPFqP+bzBVAaam9F4g8zHH4ltLs68l1otnVk3TBgH8SlZBwjsdUyKr7WQHot R7nskd51Lc7i9yjgZACvaPuUIs1UugsD1LBd30az2thUVkAbVdw32vqgQaIum6ZATVgb 9qApuVVLa9/TkbXnn1EiKdEEu0JS+olnI+C0UZzBNr94USa7iOl1M/2ND9fsgkvp3xyg 8SAOstq54RRSlXATga6W4lTDxSdxl7CC/pnBJbTjtmx1asyjGZD6/fWTO54TNxLvBwz8 SMzQ== X-Gm-Message-State: AIVw111CH0+BPTEFSQeJ+lqfXlmjQb5QKGAv2dhpFajuQKDs8seNMJEV oD2f733RfAned/wCnQw= X-Received: by 10.84.164.193 with SMTP id l1mr22432499plg.106.1500139857638; Sat, 15 Jul 2017 10:30:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Jul 2017 07:30:43 -1000 Message-Id: <20170715173050.31018-2-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715173050.31018-1-rth@twiddle.net> References: <20170715173050.31018-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PULL 1/8] target/s390x: Implement CSST X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- target/s390x/helper.h | 1 + target/s390x/cpu_models.c | 2 + target/s390x/mem_helper.c | 189 +++++++++++++++++++++++++++++++++++++++++= ++++ target/s390x/translate.c | 13 +++- target/s390x/insn-data.def | 2 + 5 files changed, 206 insertions(+), 1 deletion(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 964097b..23e8d1d 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -33,6 +33,7 @@ DEF_HELPER_3(celgb, i64, env, i64, i32) DEF_HELPER_3(cdlgb, i64, env, i64, i32) DEF_HELPER_3(cxlgb, i64, env, i64, i32) DEF_HELPER_4(cdsg, void, env, i64, i32, i32) +DEF_HELPER_4(csst, i32, env, i32, i64, i64) DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(adb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_5(axb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c index c654279..8433010 100644 --- a/target/s390x/cpu_models.c +++ b/target/s390x/cpu_models.c @@ -787,6 +787,8 @@ static void add_qemu_cpu_model_features(S390FeatBitmap = fbm) S390_FEAT_ETF2_ENH, S390_FEAT_STORE_CLOCK_FAST, S390_FEAT_MOVE_WITH_OPTIONAL_SPEC, + S390_FEAT_COMPARE_AND_SWAP_AND_STORE, + S390_FEAT_COMPARE_AND_SWAP_AND_STORE_2, S390_FEAT_GENERAL_INSTRUCTIONS_EXT, S390_FEAT_EXECUTE_EXT, S390_FEAT_FLOATING_POINT_SUPPPORT_ENH, diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index ede8471..513b402 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1353,6 +1353,195 @@ void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, env->regs[r1 + 1] =3D int128_getlo(oldv); } =20 +uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64= _t a2) +{ +#if !defined(CONFIG_USER_ONLY) || defined(CONFIG_ATOMIC128) + uint32_t mem_idx =3D cpu_mmu_index(env, false); +#endif + uintptr_t ra =3D GETPC(); + uint32_t fc =3D extract32(env->regs[0], 0, 8); + uint32_t sc =3D extract32(env->regs[0], 8, 8); + uint64_t pl =3D get_address(env, 1) & -16; + uint64_t svh, svl; + uint32_t cc; + + /* Sanity check the function code and storage characteristic. */ + if (fc > 1 || sc > 3) { + if (!s390_has_feat(S390_FEAT_COMPARE_AND_SWAP_AND_STORE_2)) { + goto spec_exception; + } + if (fc > 2 || sc > 4 || (fc =3D=3D 2 && (r3 & 1))) { + goto spec_exception; + } + } + + /* Sanity check the alignments. */ + if (extract32(a1, 0, 4 << fc) || extract32(a2, 0, 1 << sc)) { + goto spec_exception; + } + + /* Sanity check writability of the store address. */ +#ifndef CONFIG_USER_ONLY + probe_write(env, a2, mem_idx, ra); +#endif + + /* Note that the compare-and-swap is atomic, and the store is atomic, = but + the complete operation is not. Therefore we do not need to assert = serial + context in order to implement this. That said, restart early if we= can't + support either operation that is supposed to be atomic. */ + if (parallel_cpus) { + int mask =3D 0; +#if !defined(CONFIG_ATOMIC64) + mask =3D -8; +#elif !defined(CONFIG_ATOMIC128) + mask =3D -16; +#endif + if (((4 << fc) | (1 << sc)) & mask) { + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + } + } + + /* All loads happen before all stores. For simplicity, load the entire + store value area from the parameter list. */ + svh =3D cpu_ldq_data_ra(env, pl + 16, ra); + svl =3D cpu_ldq_data_ra(env, pl + 24, ra); + + switch (fc) { + case 0: + { + uint32_t nv =3D cpu_ldl_data_ra(env, pl, ra); + uint32_t cv =3D env->regs[r3]; + uint32_t ov; + + if (parallel_cpus) { +#ifdef CONFIG_USER_ONLY + uint32_t *haddr =3D g2h(a1); + ov =3D atomic_cmpxchg__nocheck(haddr, cv, nv); +#else + TCGMemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mem_= idx); + ov =3D helper_atomic_cmpxchgl_be_mmu(env, a1, cv, nv, oi, = ra); +#endif + } else { + ov =3D cpu_ldl_data_ra(env, a1, ra); + cpu_stl_data_ra(env, a1, (ov =3D=3D cv ? nv : ov), ra); + } + cc =3D (ov !=3D cv); + env->regs[r3] =3D deposit64(env->regs[r3], 32, 32, ov); + } + break; + + case 1: + { + uint64_t nv =3D cpu_ldq_data_ra(env, pl, ra); + uint64_t cv =3D env->regs[r3]; + uint64_t ov; + + if (parallel_cpus) { +#ifdef CONFIG_USER_ONLY +# ifdef CONFIG_ATOMIC64 + uint64_t *haddr =3D g2h(a1); + ov =3D atomic_cmpxchg__nocheck(haddr, cv, nv); +# else + /* Note that we asserted !parallel_cpus above. */ + g_assert_not_reached(); +# endif +#else + TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN, mem_i= dx); + ov =3D helper_atomic_cmpxchgq_be_mmu(env, a1, cv, nv, oi, = ra); +#endif + } else { + ov =3D cpu_ldq_data_ra(env, a1, ra); + cpu_stq_data_ra(env, a1, (ov =3D=3D cv ? nv : ov), ra); + } + cc =3D (ov !=3D cv); + env->regs[r3] =3D ov; + } + break; + + case 2: + { + uint64_t nvh =3D cpu_ldq_data_ra(env, pl, ra); + uint64_t nvl =3D cpu_ldq_data_ra(env, pl + 8, ra); + Int128 nv =3D int128_make128(nvl, nvh); + Int128 cv =3D int128_make128(env->regs[r3 + 1], env->regs[r3]); + Int128 ov; + + if (parallel_cpus) { +#ifdef CONFIG_ATOMIC128 + TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, me= m_idx); + ov =3D helper_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, = ra); + cc =3D !int128_eq(ov, cv); +#else + /* Note that we asserted !parallel_cpus above. */ + g_assert_not_reached(); +#endif + } else { + uint64_t oh =3D cpu_ldq_data_ra(env, a1 + 0, ra); + uint64_t ol =3D cpu_ldq_data_ra(env, a1 + 8, ra); + + ov =3D int128_make128(ol, oh); + cc =3D !int128_eq(ov, cv); + if (cc) { + nv =3D ov; + } + + cpu_stq_data_ra(env, a1 + 0, int128_gethi(nv), ra); + cpu_stq_data_ra(env, a1 + 8, int128_getlo(nv), ra); + } + + env->regs[r3 + 0] =3D int128_gethi(ov); + env->regs[r3 + 1] =3D int128_getlo(ov); + } + break; + + default: + g_assert_not_reached(); + } + + /* Store only if the comparison succeeded. Note that above we use a p= air + of 64-bit big-endian loads, so for sc < 3 we must extract the value + from the most-significant bits of svh. */ + if (cc =3D=3D 0) { + switch (sc) { + case 0: + cpu_stb_data_ra(env, a2, svh >> 56, ra); + break; + case 1: + cpu_stw_data_ra(env, a2, svh >> 48, ra); + break; + case 2: + cpu_stl_data_ra(env, a2, svh >> 32, ra); + break; + case 3: + cpu_stq_data_ra(env, a2, svh, ra); + break; + case 4: + if (parallel_cpus) { +#ifdef CONFIG_ATOMIC128 + TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, me= m_idx); + Int128 sv =3D int128_make128(svl, svh); + helper_atomic_sto_be_mmu(env, a2, sv, oi, ra); +#else + /* Note that we asserted !parallel_cpus above. */ + g_assert_not_reached(); +#endif + } else { + cpu_stq_data_ra(env, a2 + 0, svh, ra); + cpu_stq_data_ra(env, a2 + 8, svl, ra); + } + default: + g_assert_not_reached(); + } + } + + return cc; + + spec_exception: + cpu_restore_state(ENV_GET_CPU(env), ra); + program_interrupt(env, PGM_SPECIFICATION, 6); + g_assert_not_reached(); +} + #if !defined(CONFIG_USER_ONLY) void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t = r3) { diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 592d6b0..e739525 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -2033,6 +2033,18 @@ static ExitStatus op_cdsg(DisasContext *s, DisasOps = *o) return NO_EXIT; } =20 +static ExitStatus op_csst(DisasContext *s, DisasOps *o) +{ + int r3 =3D get_field(s->fields, r3); + TCGv_i32 t_r3 =3D tcg_const_i32(r3); + + gen_helper_csst(cc_op, cpu_env, t_r3, o->in1, o->in2); + tcg_temp_free_i32(t_r3); + + set_cc_static(s); + return NO_EXIT; +} + #ifndef CONFIG_USER_ONLY static ExitStatus op_csp(DisasContext *s, DisasOps *o) { @@ -5437,7 +5449,6 @@ enum DisasInsnEnum { /* Give smaller names to the various facilities. */ #define FAC_Z S390_FEAT_ZARCH #define FAC_CASS S390_FEAT_COMPARE_AND_SWAP_AND_STORE -#define FAC_CASS2 S390_FEAT_COMPARE_AND_SWAP_AND_STORE_2 #define FAC_DFP S390_FEAT_DFP #define FAC_DFPR S390_FEAT_FLOATING_POINT_SUPPPORT_ENH /* DFP-round= ing */ #define FAC_DO S390_FEAT_STFLE_45 /* distinct-operands */ diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index d3bb851..6ac12b8 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -265,6 +265,8 @@ D(0xbb00, CDS, RS_a, Z, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_= TEQ) D(0xeb31, CDSY, RSY_a, LD, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_= TEQ) C(0xeb3e, CDSG, RSY_a, Z, 0, 0, 0, 0, cdsg, 0) +/* COMPARE AND SWAP AND STORE */ + C(0xc802, CSST, SSF, CASS, la1, a2, 0, 0, csst, 0) =20 /* COMPARE AND TRAP */ D(0xb972, CRT, RRF_c, GIE, r1_32s, r2_32s, 0, 0, ct, 0, 0) --=20 2.9.4