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[173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zyEtXDWfeoQZUHVKSmzuldu8S8sl26LD5I2ouLjZIbc=; b=h2re/hphCO6+G0/YNX/BC8XoVQG+svBa4/bI3Y8WcSZL7vji/q82D6ViuuVFdAlwLO 2u5W/EDtWRTpHtjyZLRm1NeOC8hkkNEuyKCWgkaLgNqFa9WzZwZCikM6O4CzwZtWQ/5j dUFzRBALqywoo/14Bfz31Nm3f88pLfDvZxB2UkXwrFKd2ALOFoJGlVXKmd6pIPgpCIvK j+HICkWKehemQ5p4E6Ff6VdITy7XGS4bDYRjjU6PqlcOSmFuaCxjlcvqYcj1ZpqCym9J LR49im1URpxaGAtbrFB8C2uqOaYE/qWNq2D5TO86fITs06EQrzrlNgAzwfBhvvbRozz3 itMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=zyEtXDWfeoQZUHVKSmzuldu8S8sl26LD5I2ouLjZIbc=; b=NnAMVcUjeglsn0b/r2tx5w8H/2MiBQqJDFMJ7yN835OpuRERx25kOLfrvK/Np+SA7a tFIn4px+MBzZRdcMjSoEZmtD2IUO4nOpnd0pGXBwbWW823T+ehr1iQFjZae1zK8YwWiS IZqyrPhweWIQ9tu4Cjc2EWevhEPZRQlEaV2wkmNu8adz2NOH19k8AD3VLUczzw8jfM3z eXQkxQvSKFq3rhH1OfIhtqDoCPDBkVD6ngbbN/PNeOuD68uUMudHuQhU4nAgYTss5EJ1 qZKHxVMRNEog4g6rnYq5jIYggkCoGvPN6kBbJrO2HdRUpZMEWen65bBu2H+gcScZJnhH 6YDA== X-Gm-Message-State: AIVw113e6s0uvzUaBwBggfTI/X34aE8lW1/iebQzgGbIkoBoLH/MpQoM Riuj5KVVHodufmNWCIE= X-Received: by 10.98.95.67 with SMTP id t64mr9627121pfb.127.1500111820578; Sat, 15 Jul 2017 02:43:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:34 -1000 Message-Id: <20170715094243.28371-26-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v14 25/34] target/arm: [tcg, a64] Port to translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002510079.22386.10164419868911710218.stgit@frigg.lan> [rth: Adjust for translate_insn interface change.] Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++++--------------= ---- 1 file changed, 43 insertions(+), 28 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1541bf0..a92a3ec 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11244,6 +11244,9 @@ static int aarch64_tr_init_disas_context(DisasConte= xtBase *dcbase, dc->is_ldex =3D false; dc->ss_same_el =3D (arm_debug_target_el(env) =3D=3D dc->current_el); =20 + dc->next_page_start =3D + (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; + init_tmp_a64_array(dc); =20 return max_insns; @@ -11281,12 +11284,43 @@ static bool aarch64_tr_breakpoint_check(DisasCont= extBase *dcbase, CPUState *cpu, return true; } =20 +static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *= cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUARMState *env =3D cpu->env_ptr; + + if (dc->ss_active && !dc->pstate_ss) { + /* Singlestep state is Active-pending. + * If we're in this state at the start of a TB then either + * a) we just took an exception to an EL which is being debugged + * and this is the first insn in the exception handler + * b) debug exceptions were masked and we just unmasked them + * without changing EL (eg by clearing PSTATE.D) + * In either case we're going to take a swstep exception in the + * "did not step an insn" case, and so the syndrome ISV and EX + * bits should be zero. + */ + assert(dc->base.num_insns =3D=3D 1); + gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), + default_exception_el(dc)); + dc->base.is_jmp =3D DISAS_NORETURN; + } else { + disas_a64_insn(env, dc); + } + + if (dc->base.is_jmp =3D=3D DISAS_NEXT) { + if (dc->ss_active || dc->pc >=3D dc->next_page_start) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + } + + dc->base.pc_next =3D dc->pc; +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { - CPUARMState *env =3D cs->env_ptr; DisasContext *dc =3D container_of(dcbase, DisasContext, base); - target_ulong next_page_start; int max_insns; =20 dc->base.tb =3D tb; @@ -11296,7 +11330,6 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, dc->base.num_insns =3D 0; dc->base.singlestep_enabled =3D cs->singlestep_enabled; =20 - next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D dc->base.tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -11332,42 +11365,24 @@ void gen_intermediate_code_a64(DisasContextBase *= dcbase, CPUState *cs, gen_io_start(); } =20 - if (dc->ss_active && !dc->pstate_ss) { - /* Singlestep state is Active-pending. - * If we're in this state at the start of a TB then either - * a) we just took an exception to an EL which is being debug= ged - * and this is the first insn in the exception handler - * b) debug exceptions were masked and we just unmasked them - * without changing EL (eg by clearing PSTATE.D) - * In either case we're going to take a swstep exception in the - * "did not step an insn" case, and so the syndrome ISV and EX - * bits should be zero. - */ - assert(dc->base.num_insns =3D=3D 1); - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), - default_exception_el(dc)); - dc->base.is_jmp =3D DISAS_NORETURN; - break; - } - - disas_a64_insn(env, dc); + aarch64_tr_translate_insn(&dc->base, cs); =20 if (tcg_check_temp_count()) { fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", dc->pc); } =20 + if (!dc->base.is_jmp && (tcg_op_buf_full() || cs->singlestep_enabl= ed || + singlestep || dc->base.num_insns >=3D max_insn= s)) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + /* Translation stops when a conditional branch is encountered. * Otherwise the subsequent code could get translated several time= s. * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - } while (!dc->base.is_jmp && !tcg_op_buf_full() && - !cs->singlestep_enabled && - !singlestep && - !dc->ss_active && - dc->pc < next_page_start && - dc->base.num_insns < max_insns); + } while (!dc->base.is_jmp); =20 if (dc->base.tb->cflags & CF_LAST_IO) { gen_io_end(); --=20 2.9.4