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[173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JzDraqfJlm6zr+oB9vjFRKwS1eMbCDVypDaKvzqeD8g=; b=W+hz/1NlILp7IDUB5erDUo7oSO7a3YB0SqBH5UVrgRD//vzD7d3y9pMjs4qZKqY68o vEtmnSdexDYgYhb5SJisvRcCOzuHa0QduPDgn3nPXsfE6PlvkCnWjwBpZSftL5CDmLNx g4znYvsu/MjHpKv+7Vs/hRlYqAcdWhgvPXeW3qcINg8IEirE4fziCgv7n/IKRYfLFAnU 0gWh4WoZeeHnBSKX+YdgsBc5c3bGo4CXUr0QoqD9T2S0JUA6LKWQD+hhezyYgKHa9Py+ shNKYD5Liz4CqRFDQFtkPm26LATAI0f7p6xbZlrITxnPade57PQiLkZySRNuC7nBJVcl I16A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=JzDraqfJlm6zr+oB9vjFRKwS1eMbCDVypDaKvzqeD8g=; b=PPLCjliqMT9TjxQF/u8CxHBIEOq5/NSaANaQI8xBvWTxX1gMO8c7dx8QIA/QMbkFA8 9LjilBzgVeOTieWaUYsVlnvsXCnxroBdotPxJDzYFF7QIGyJKMEzZQBgAAaenltwQrRG slLEz1GDmIM5SJn+OHa5cmbN/VR4SYtXrErgkkP5B+W7RxeowGkZ9JZcyz3qLsEneAGR 2kqjMyKX4oYJyLEKmzB5dIt8wkBAVVZS+fbK1snO/727Mw/15mlc67HWA/giajGvqznh X+YltMo8RlHAcHPxJh8AKhE6kDHr2UEzbGRlbzDt7uXbn+0UVDF/NqiPaNV5s0te5xxZ s3sQ== X-Gm-Message-State: AIVw110B3kafI4hd4MfTCUmwKdvblz6CH6Exh3LXxPWE6ZxKR01qU/+G BlOePHQGtUgfl0ikB7k= X-Received: by 10.101.91.15 with SMTP id y15mr19579183pgq.88.1500111814896; Sat, 15 Jul 2017 02:43:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:31 -1000 Message-Id: <20170715094243.28371-23-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v14 22/34] target/arm: [tcg, a64] Port to insn_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002413187.22386.156315485813606121.stgit@frigg.lan> [rth: Use DISAS_TOO_MANY for "execute only one more" after bp.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 11 +++++++-- target/arm/translate.c | 56 +++++++++++++++++++++++++++++-------------= ---- 2 files changed, 44 insertions(+), 23 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e9bea91..dca5825 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11249,6 +11249,14 @@ static int aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, return max_insns; } =20 +static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + dc->insn_start_idx =3D tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, 0, 0); +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11280,8 +11288,7 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, =20 do { dc->base.num_insns++; - dc->insn_start_idx =3D tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, 0, 0); + aarch64_tr_insn_start(&dc->base, cs); =20 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; diff --git a/target/arm/translate.c b/target/arm/translate.c index 5e09682..15bd9e7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11908,6 +11908,33 @@ static void arm_tr_insn_start(DisasContextBase *dc= base, CPUState *cpu) 0); } =20 +static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cp= u, + const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + if (bp->flags & BP_CPU) { + gen_set_condexec(dc); + gen_set_pc_im(dc, dc->pc); + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it's likely not going to be executed */ + dc->base.is_jmp =3D DISAS_TOO_MANY; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* The address covered by the breakpoint must be + included in [tb->pc, tb->pc + tb->size) in order + to for it to be properly cleared -- thus we + increment the PC here so that the logic setting + tb->size below does the right thing. */ + /* TODO: Advance PC by correct instruction length to + * avoid disassembler error messages */ + dc->pc +=3D 2; + dc->base.is_jmp =3D DISAS_NORETURN; + } + + return true; +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -11956,29 +11983,15 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->pc) { - if (bp->flags & BP_CPU) { - gen_set_condexec(dc); - gen_set_pc_im(dc, dc->pc); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it's likely not going to be e= xecuted */ - dc->base.is_jmp =3D DISAS_UPDATE; - } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - dc->base.is_jmp =3D DISAS_NORETURN; - /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - tb->size below does the right thing. */ - /* TODO: Advance PC by correct instruction length = to - * avoid disassembler error messages */ - dc->pc +=3D 2; - goto done_generating; + if (bp->pc =3D=3D dc->base.pc_next) { + if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { + break; } - break; } } + if (dc->base.is_jmp > DISAS_TOO_MANY) { + break; + } } =20 if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { @@ -12100,6 +12113,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) gen_exception(EXCP_SMC, syn_aa32_smc(), 3); break; case DISAS_NEXT: + case DISAS_TOO_MANY: case DISAS_UPDATE: gen_set_pc_im(dc, dc->pc); /* fall through */ @@ -12120,6 +12134,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) */ switch(dc->base.is_jmp) { case DISAS_NEXT: + case DISAS_TOO_MANY: gen_goto_tb(dc, 1, dc->pc); break; case DISAS_UPDATE: @@ -12173,7 +12188,6 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) } } =20 -done_generating: gen_tb_end(tb, dc->base.num_insns); =20 #ifdef DEBUG_DISAS --=20 2.9.4