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[173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VDR1caK9PH2mHP3KczBdrLfwciXkpit7/DT6v8fS6tA=; b=g5Rw6LvdjsDAAIN0Wg55DzR1rvP9VNNEjkLAOFqselHSj+T5+R0JpVDoB3AnToXO1g Qu6B2pkP1SMcsrOmBsI8fl9NR2pi7zH7IVjyRlNufbBpBO4HUf6wrcJDS3Z5KDyEjSwA /ZsPYuuY3SJ9aBTpJoyYROSA2+t9nm9lTQrfjQTaNeAfsRylVhHU3Fj5JNSBQNg2ZT8i cfqttP/FIVmIZt2O0jrL0o6s+sq6GyJvlBI+ZS9ylpoitME12bVWrLHjS836jb0MEjWf haNfJUe9ueLaIyJVt+VmcpS/pkRYKwT61mBYVj+vkL0yq6wLaEzwk6PaQ7siILZCCBw+ nxxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=VDR1caK9PH2mHP3KczBdrLfwciXkpit7/DT6v8fS6tA=; b=eeaDUJdAAj6sO7avVy8DGzLjRwJYZoqhzLFnJgg8iMH5ozZ/mzGfkVEPDvDd82HiM2 gAcX28VP+BIoOo3g7WPrLKGgShmMuvUy1GU44zowCTYt4bSeCi3QOfY2dbjiNzf4CH0P qnZQ2HaN38y6sn4oPHSE98we2An8YeJJB5TEb/KMow+QoAKpXoMV2uZ8M6nh7YxM13Bl fX9iIMrqokTZ2VRGrzXH7JU/BOC9WHFOpf0edx5wii7NWuX960VCAOhwEDyEkwWP+VGd fAPeIy3a8M8Cyn9FY5wQST6R1qrP1IFgUgdN6XO0Z1V5lun4eRfPskxn4ScMH/5c91BN Y+pA== X-Gm-Message-State: AIVw113qCRZWt4PCOtN6nb1EH5LBFwncZBAO+89rDIUg9nerKDpL/xVM uhwrXoQ5Qfz3cn3eD00= X-Received: by 10.98.75.73 with SMTP id y70mr1528230pfa.167.1500111810973; Sat, 15 Jul 2017 02:43:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:29 -1000 Message-Id: <20170715094243.28371-21-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v14 20/34] target/arm: [tcg] Port to tb_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002364681.22386.1701754996184325808.stgit@frigg.lan> [rth: Adjust for tb_start interface change.] Signed-off-by: Richard Henderson --- target/arm/translate.c | 82 +++++++++++++++++++++++++++-------------------= ---- 1 file changed, 44 insertions(+), 38 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index de9c456..f5d69db 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11855,6 +11855,49 @@ static int arm_tr_init_disas_context(DisasContextB= ase *dcbase, return max_insns; } =20 +static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + /* A note on handling of the condexec (IT) bits: + * + * We want to avoid the overhead of having to write the updated condex= ec + * bits back to the CPUARMState for every instruction in an IT block. = So: + * (1) if the condexec bits are not already zero then we write + * zero back into the CPUARMState now. This avoids complications trying + * to do it at the end of the block. (For example if we don't do this + * it's hard to identify whether we can safely skip writing condexec + * at the end of the TB, which we definitely want to do for the case + * where a TB doesn't do anything with the IT state at all.) + * (2) if we are going to leave the TB then we call gen_set_condexec() + * which will write the correct value into CPUARMState if zero is wron= g. + * This is done both for leaving the TB at the end, and for leaving + * it because of an exception we know will happen, which is done in + * gen_exception_insn(). The latter is necessary because we need to + * leave the TB with the PC/IT state just prior to execution of the + * instruction which caused the exception. + * (3) if we leave the TB unexpectedly (eg a data abort on a load) + * then the CPUARMState will be wrong and we need to reset it. + * This is handled in the same way as restoration of the + * PC in these situations; we save the value of the condexec bits + * for each PC via tcg_gen_insn_start(), and restore_state_to_opc() + * then uses this to restore them after an exception. + * + * Note that there are no instructions which can read the condexec + * bits, and none which can write non-static values to them, so + * we don't need to care about whether CPUARMState is correct in the + * middle of a TB. + */ + + /* Reset the conditional execution bits immediately. This avoids + complications trying to do it at the end of the block. */ + if (dc->condexec_mask || dc->condexec_cond) { + TCGv_i32 tmp =3D tcg_temp_new_i32(); + tcg_gen_movi_i32(tmp, 0); + store_cpu_field(tmp, condexec_bits); + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -11894,45 +11937,8 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) gen_tb_start(tb); =20 tcg_clear_temp_count(); + arm_tr_tb_start(&dc->base, cs); =20 - /* A note on handling of the condexec (IT) bits: - * - * We want to avoid the overhead of having to write the updated condex= ec - * bits back to the CPUARMState for every instruction in an IT block. = So: - * (1) if the condexec bits are not already zero then we write - * zero back into the CPUARMState now. This avoids complications trying - * to do it at the end of the block. (For example if we don't do this - * it's hard to identify whether we can safely skip writing condexec - * at the end of the TB, which we definitely want to do for the case - * where a TB doesn't do anything with the IT state at all.) - * (2) if we are going to leave the TB then we call gen_set_condexec() - * which will write the correct value into CPUARMState if zero is wron= g. - * This is done both for leaving the TB at the end, and for leaving - * it because of an exception we know will happen, which is done in - * gen_exception_insn(). The latter is necessary because we need to - * leave the TB with the PC/IT state just prior to execution of the - * instruction which caused the exception. - * (3) if we leave the TB unexpectedly (eg a data abort on a load) - * then the CPUARMState will be wrong and we need to reset it. - * This is handled in the same way as restoration of the - * PC in these situations; we save the value of the condexec bits - * for each PC via tcg_gen_insn_start(), and restore_state_to_opc() - * then uses this to restore them after an exception. - * - * Note that there are no instructions which can read the condexec - * bits, and none which can write non-static values to them, so - * we don't need to care about whether CPUARMState is correct in the - * middle of a TB. - */ - - /* Reset the conditional execution bits immediately. This avoids - complications trying to do it at the end of the block. */ - if (dc->condexec_mask || dc->condexec_cond) - { - TCGv_i32 tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - store_cpu_field(tmp, condexec_bits); - } do { dc->base.num_insns++; dc->insn_start_idx =3D tcg_op_buf_count(); --=20 2.9.4