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[173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fdP2kzvaD6CiKuNH4AM+/FTEXyCuSKlT/dRMCpWRSOk=; b=JziHnWsw7hdEGri6rwBnDGf0Tp5SvDLIuNODXaluNwoOAZTDtAVGC+j+WDDItZhZlN kfitDuu+dVlQ/TV6dBIKp1OZcbholE9rS9mX7t96dXspK89+uYWtVioXgvG7oKRYL7hn SKpXHGHKN+zO20E2NvgRXgkOYZHXn0RuOVEYVVc3zYzuowTXfrk1RGSsOkZtf1K8xUms Sz5Y9/lTn11ZS68OlGXoS8LtNg6QJDClGGJu92DQEtst/V1qqYVc0siSBpGilopP/lLg xG0RPxq1Nfjo6AK7PgluCt+STFnqzHbL7mWwhQLQHYUEb6lzR0SYxfFwX7w4lfaz2KVp MuCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fdP2kzvaD6CiKuNH4AM+/FTEXyCuSKlT/dRMCpWRSOk=; b=lzLk50Jj+ycgyKhchcoV7bReIo5zQ5guHR3g5SO7A0uUS16vEaLtAkDVaVKMmPar3h /F6REyO+MQqdsvDE7yHJSPtBieG0YClx8ddxsmWRA9UIi//Aa5DhSOT3tc5HPXZxtJxZ kx5aUDgN2J1yJeUzHrSiF56Bm9X/53cHf0j23EKbiH4RYdLNtLJkRNHLRX8pZofT7Fmv XoPcQhWY6q9npA0uhb+ImF56x9qz5HN6/qgtBN62ay9AA4/HfbUkzQ5nrej0Mo/kjwXz 9lJMOZbb+y8UDdPIZIanAQgN8txIHVPwD5/DRv0hhfNgF8qF3KmZNkY4bL8pXm83pH+3 kDOg== X-Gm-Message-State: AIVw113P26Q2xWs9GmK+EQ71OlPSGqV93knZpe7a7EzjNnQDdLec4jBI LpydKq1bctnVuHyoe40= X-Received: by 10.98.150.135 with SMTP id s7mr9780744pfk.172.1500111794653; Sat, 15 Jul 2017 02:43:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:21 -1000 Message-Id: <20170715094243.28371-13-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v14 12/34] target/i386: [tcg] Port to breakpoint_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Emilio G. Cota Message-Id: <150002170871.22386.2172835658104140576.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 46 ++++++++++++++++++++++++++++++++++------------ 1 file changed, 34 insertions(+), 12 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 6e1243a..a009710 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8455,6 +8455,26 @@ static void i386_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); } =20 +static bool i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *c= pu, + const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + /* If RF is set, suppress an internally generated breakpoint. */ + int flags =3D dc->base.tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY; + if (bp->flags & flags) { + gen_debug(dc, dc->base.pc_next - dc->cs_base); + dc->base.is_jmp =3D DISAS_NORETURN; + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + dc->base.pc_next +=3D 1; + return true; + } else { + return false; + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -8485,18 +8505,21 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) i386_tr_insn_start(&dc->base, cs); num_insns++; =20 - /* If RF is set, suppress an internally generated breakpoint. */ - if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, - tb->flags & HF_RF_MASK - ? BP_GDB : BP_ANY))) { - gen_debug(dc, dc->base.pc_next - dc->cs_base); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->base.pc_next +=3D 1; - goto done_generating; + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + CPUBreakpoint *bp; + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + if (bp->pc =3D=3D dc->base.pc_next) { + if (i386_tr_breakpoint_check(&dc->base, cs, bp)) { + break; + } + } + } + + if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { + break; + } } + if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } @@ -8547,7 +8570,6 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) } if (tb->cflags & CF_LAST_IO) gen_io_end(); -done_generating: gen_tb_end(tb, num_insns); =20 #ifdef DEBUG_DISAS --=20 2.9.4