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[173.197.98.123]) by smtp.gmail.com with ESMTPSA id v47sm5647206qtb.11.2017.07.13.17.18.34 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jul 2017 17:18:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=480lmbGrgiFOMg91D1Og3w231M3L5MOzmFc2WpmR/MU=; b=H7XC56mWkBU9sXEjOaUNy3MRqoM4AoAaFxI62oqY7ESpqeKiWaQfDC7piRjvySB9RU 3hT9rpEtc8c4Trlhq+ukJSdEmw80JcNy8Btjxyvasl/X09rvU46o6PXzYas/vHG+I7U0 dzydVX0nJZGQhalSEvra8avLadqK+WtXWR7HSc4u4m9R5M2WXwBuBqkTjWgT03Sm75zH WCRmLRGMUzo+N3SRphIkTk4XS6GXa1C2v3hSraG7zye8GSwnKmvhZBtAwbBGPcGkwm0B FKEsp0iDQppMbMs40jm/2tJE1C2JsvtzJz9IvnsicKGeNseiJQmb2fNarTDbybkQCSQn WsUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=480lmbGrgiFOMg91D1Og3w231M3L5MOzmFc2WpmR/MU=; b=SxmnqIATke7MQSClxChk9vjPh3Merra/FPOXPUByviY2AUgvNeaxLuUjUa0wK/Q8p0 flcX+QjGUQtqTAmvdC9t8dY3TnnY1QUTZJt95EJMyFz74ydoJnB8IQUYVPJu/G/8gpcj D/T7HGj6YNt4r+NgH8jJ0zUqJLCI5CQrRpDjwJKICUDfo90UqFeK1k4IunmL1U5WmOYE f3r5vu4RyexQ/Vc+2ZcW5XMNkFyVtAlfxyxcGLwtTb7zegfKtgIgVHh9iW7BZiateqel qGM0JL3aza0P6LjxVi/CVQLgUglvU3w7XixEz7DawAokWvun/h6gh8S0fWApWbsUg+4u ToCA== X-Gm-Message-State: AIVw113Tzp9MThuguMhHkSDuRlgB9bXNMgo6lUt5AmybVPE4N4K6ASMa r0CyMREhgYdl85CUIcQ= X-Received: by 10.233.232.212 with SMTP id a203mr7600721qkg.261.1499991515932; Thu, 13 Jul 2017 17:18:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Jul 2017 14:18:12 -1000 Message-Id: <20170714001819.1660-2-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170714001819.1660-1-rth@twiddle.net> References: <20170714001819.1660-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH 1/8] target/alpha: Remove amask from tb->flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This value is constant for the cpu and does not need to be stored within the TB. Signed-off-by: Richard Henderson Tested-by: Emilio G. Cota --- target/alpha/cpu.h | 9 ------- target/alpha/translate.c | 70 ++++++++++++++++++++++++++------------------= ---- 2 files changed, 38 insertions(+), 41 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 691ac00..aa83417 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -487,14 +487,6 @@ enum { TB_FLAGS_PAL_MODE =3D 1, TB_FLAGS_FEN =3D 2, TB_FLAGS_USER_MODE =3D 8, - - TB_FLAGS_AMASK_SHIFT =3D 4, - TB_FLAGS_AMASK_BWX =3D AMASK_BWX << TB_FLAGS_AMASK_SHIFT, - TB_FLAGS_AMASK_FIX =3D AMASK_FIX << TB_FLAGS_AMASK_SHIFT, - TB_FLAGS_AMASK_CIX =3D AMASK_CIX << TB_FLAGS_AMASK_SHIFT, - TB_FLAGS_AMASK_MVI =3D AMASK_MVI << TB_FLAGS_AMASK_SHIFT, - TB_FLAGS_AMASK_TRAP =3D AMASK_TRAP << TB_FLAGS_AMASK_SHIFT, - TB_FLAGS_AMASK_PREFETCH =3D AMASK_PREFETCH << TB_FLAGS_AMASK_SHIFT, }; =20 static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *= pc, @@ -513,7 +505,6 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *= env, target_ulong *pc, if (env->fen) { flags |=3D TB_FLAGS_FEN; } - flags |=3D env->amask << TB_FLAGS_AMASK_SHIFT; =20 *pflags =3D flags; } diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 232af9e..4a627fc 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -51,14 +51,15 @@ struct DisasContext { #endif int mem_idx; =20 + /* implver and amask values for this CPU. */ + int implver; + int amask; + /* Current rounding mode for this TB. */ int tb_rm; /* Current flush-to-zero setting for this TB. */ int tb_ftz; =20 - /* implver value for this CPU. */ - int implver; - /* The set of registers active in the current context. */ TCGv *ir; =20 @@ -1442,6 +1443,13 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv v= b, int regno) } \ } while (0) =20 +#define REQUIRE_AMASK(FLAG) \ + do { \ + if ((ctx->amask & AMASK_##FLAG) =3D=3D 0) { \ + goto invalid_opc; \ + } \ + } while (0) + #define REQUIRE_TB_FLAG(FLAG) \ do { \ if ((ctx->tb->flags & (FLAG)) =3D=3D 0) { \ @@ -1532,7 +1540,7 @@ static ExitStatus translate_one(DisasContext *ctx, ui= nt32_t insn) =20 case 0x0A: /* LDBU */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); + REQUIRE_AMASK(BWX); gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0); break; case 0x0B: @@ -1541,17 +1549,17 @@ static ExitStatus translate_one(DisasContext *ctx, = uint32_t insn) break; case 0x0C: /* LDWU */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); + REQUIRE_AMASK(BWX); gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0); break; case 0x0D: /* STW */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); + REQUIRE_AMASK(BWX); gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0); break; case 0x0E: /* STB */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); + REQUIRE_AMASK(BWX); gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0); break; case 0x0F: @@ -1832,10 +1840,7 @@ static ExitStatus translate_one(DisasContext *ctx, u= int32_t insn) case 0x61: /* AMASK */ REQUIRE_REG_31(ra); - { - uint64_t amask =3D ctx->tb->flags >> TB_FLAGS_AMASK_SHIFT; - tcg_gen_andi_i64(vc, vb, ~amask); - } + tcg_gen_andi_i64(vc, vb, ~ctx->amask); break; case 0x64: /* CMOVLE */ @@ -2048,7 +2053,7 @@ static ExitStatus translate_one(DisasContext *ctx, ui= nt32_t insn) break; =20 case 0x14: - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX); + REQUIRE_AMASK(FIX); vc =3D dest_fpr(ctx, rc); switch (fpfn) { /* fn11 & 0x3F */ case 0x04: @@ -2525,14 +2530,14 @@ static ExitStatus translate_one(DisasContext *ctx, = uint32_t insn) vc =3D dest_gpr(ctx, rc); if (fn7 =3D=3D 0x70) { /* FTOIT */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX); + REQUIRE_AMASK(FIX); REQUIRE_REG_31(rb); va =3D load_fpr(ctx, ra); tcg_gen_mov_i64(vc, va); break; } else if (fn7 =3D=3D 0x78) { /* FTOIS */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX); + REQUIRE_AMASK(FIX); REQUIRE_REG_31(rb); t32 =3D tcg_temp_new_i32(); va =3D load_fpr(ctx, ra); @@ -2546,117 +2551,117 @@ static ExitStatus translate_one(DisasContext *ctx= , uint32_t insn) switch (fn7) { case 0x00: /* SEXTB */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); + REQUIRE_AMASK(BWX); REQUIRE_REG_31(ra); tcg_gen_ext8s_i64(vc, vb); break; case 0x01: /* SEXTW */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); + REQUIRE_AMASK(BWX); REQUIRE_REG_31(ra); tcg_gen_ext16s_i64(vc, vb); break; case 0x30: /* CTPOP */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX); + REQUIRE_AMASK(CIX); REQUIRE_REG_31(ra); REQUIRE_NO_LIT; tcg_gen_ctpop_i64(vc, vb); break; case 0x31: /* PERR */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); REQUIRE_NO_LIT; va =3D load_gpr(ctx, ra); gen_helper_perr(vc, va, vb); break; case 0x32: /* CTLZ */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX); + REQUIRE_AMASK(CIX); REQUIRE_REG_31(ra); REQUIRE_NO_LIT; tcg_gen_clzi_i64(vc, vb, 64); break; case 0x33: /* CTTZ */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX); + REQUIRE_AMASK(CIX); REQUIRE_REG_31(ra); REQUIRE_NO_LIT; tcg_gen_ctzi_i64(vc, vb, 64); break; case 0x34: /* UNPKBW */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); REQUIRE_REG_31(ra); REQUIRE_NO_LIT; gen_helper_unpkbw(vc, vb); break; case 0x35: /* UNPKBL */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); REQUIRE_REG_31(ra); REQUIRE_NO_LIT; gen_helper_unpkbl(vc, vb); break; case 0x36: /* PKWB */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); REQUIRE_REG_31(ra); REQUIRE_NO_LIT; gen_helper_pkwb(vc, vb); break; case 0x37: /* PKLB */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); REQUIRE_REG_31(ra); REQUIRE_NO_LIT; gen_helper_pklb(vc, vb); break; case 0x38: /* MINSB8 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_minsb8(vc, va, vb); break; case 0x39: /* MINSW4 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_minsw4(vc, va, vb); break; case 0x3A: /* MINUB8 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_minub8(vc, va, vb); break; case 0x3B: /* MINUW4 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_minuw4(vc, va, vb); break; case 0x3C: /* MAXUB8 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_maxub8(vc, va, vb); break; case 0x3D: /* MAXUW4 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_maxuw4(vc, va, vb); break; case 0x3E: /* MAXSB8 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_maxsb8(vc, va, vb); break; case 0x3F: /* MAXSW4 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_maxsw4(vc, va, vb); break; @@ -2929,6 +2934,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct= TranslationBlock *tb) ctx.pc =3D pc_start; ctx.mem_idx =3D cpu_mmu_index(env, false); ctx.implver =3D env->implver; + ctx.amask =3D env->amask; ctx.singlestep_enabled =3D cs->singlestep_enabled; =20 #ifdef CONFIG_USER_ONLY --=20 2.9.4 From nobody Sun Apr 28 21:11:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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[173.197.98.123]) by smtp.gmail.com with ESMTPSA id v47sm5647206qtb.11.2017.07.13.17.18.36 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jul 2017 17:18:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=MyH/0nLWVXXNnRiPPKl2NPsm9zw2LjtvFxFSROkMM6g=; b=nqhXAQlqKMsudwx1JLOWtw8m4qOPsPNMmH14kgbR9A/MTXLNJ2p0KeuCII4ETQWCc0 S1QyQPKbkXnavXxBBZ2JtpEgYZZPDx97VvxRqac7oTKplp74i1oTTAVfcNTOprVIetGI Xl/FK4/UDsG/9thSocStdRTpbzcD2XdymVQ73V2SRHuiUBWdGma85oROkBT72hGRU7Wj QyPCZfxHWh45CKJVelhzNandM3XtmBNKoeQiQ/DDmldEu5GNGqPK24nK8omCiHBBYJQS JZKqdHvaVjquKOkRlH0WPCJJqKUG9/73DzQ0RLEJ4xKXaGpKcKqPy8OIBI4gMmzAD270 afTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=MyH/0nLWVXXNnRiPPKl2NPsm9zw2LjtvFxFSROkMM6g=; b=O7GDZ9wzx0NSKfNlAqkqdMDHElNRp5mP7Vv15Vf708zVFNaSLjN3+sJSTmdXKNCwZh 0k1pRgVUUUm4eL9Z/pL3eIXW0gaLrqwK4OFvTbiXJAeIKaxpLut1p6Rz8nEEFc1cQNE8 69u76P+yCIDeyu65xMECGLPLA7HJtlHAB/MVbauV2BAFwpb+9uZK7SwZ6Bt6zb76g4Ty 6Egv/Tom43dPigI35KEZqG/gkjQ8t2PEuXeG9g8w1rQPmyNzB7R+DOtQHnXzOCX7KWK4 8GLZNDWN9kXWpf71slfNEmDBiVyejLNX2ArZOaKRMjeFch7QbwogyDQHqWJvUBI1TCfX bRqw== X-Gm-Message-State: AIVw113ay7ShHNMtNebxYgdAWGMNp2pyxJqeAhC0IyoPWtG3xRxsWng9 xBwFbNqd1jRcdaJ80gU= X-Received: by 10.55.74.13 with SMTP id x13mr8443350qka.254.1499991517551; Thu, 13 Jul 2017 17:18:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Jul 2017 14:18:13 -1000 Message-Id: <20170714001819.1660-3-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170714001819.1660-1-rth@twiddle.net> References: <20170714001819.1660-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::241 Subject: [Qemu-devel] [PATCH 2/8] target/alpha: Copy tb->flags into DisasContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Tested-by: Emilio G. Cota --- target/alpha/translate.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 4a627fc..48be19a 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -49,6 +49,7 @@ struct DisasContext { #ifndef CONFIG_USER_ONLY uint64_t palbr; #endif + uint32_t tbflags; int mem_idx; =20 /* implver and amask values for this CPU. */ @@ -452,7 +453,7 @@ static ExitStatus gen_store_conditional(DisasContext *c= tx, int ra, int rb, static bool in_superpage(DisasContext *ctx, int64_t addr) { #ifndef CONFIG_USER_ONLY - return ((ctx->tb->flags & TB_FLAGS_USER_MODE) =3D=3D 0 + return ((ctx->tbflags & TB_FLAGS_USER_MODE) =3D=3D 0 && addr >> TARGET_VIRT_ADDR_SPACE_BITS =3D=3D -1 && ((addr >> 41) & 3) =3D=3D 2); #else @@ -1167,7 +1168,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int= palcode) =20 #ifndef CONFIG_USER_ONLY /* Privileged PAL code */ - if (palcode < 0x40 && (ctx->tb->flags & TB_FLAGS_USER_MODE) =3D=3D 0) { + if (palcode < 0x40 && (ctx->tbflags & TB_FLAGS_USER_MODE) =3D=3D 0) { TCGv tmp; switch (palcode) { case 0x01: @@ -1258,7 +1259,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int= palcode) uint64_t exc_addr =3D ctx->pc; uint64_t entry =3D ctx->palbr; =20 - if (ctx->tb->flags & TB_FLAGS_PAL_MODE) { + if (ctx->tbflags & TB_FLAGS_PAL_MODE) { exc_addr |=3D 1; } else { tcg_gen_movi_i64(tmp, 1); @@ -1452,7 +1453,7 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb= , int regno) =20 #define REQUIRE_TB_FLAG(FLAG) \ do { \ - if ((ctx->tb->flags & (FLAG)) =3D=3D 0) { \ + if ((ctx->tbflags & (FLAG)) =3D=3D 0) { \ goto invalid_opc; \ } \ } while (0) @@ -2932,6 +2933,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct= TranslationBlock *tb) =20 ctx.tb =3D tb; ctx.pc =3D pc_start; + ctx.tbflags =3D tb->flags; ctx.mem_idx =3D cpu_mmu_index(env, false); ctx.implver =3D env->implver; ctx.amask =3D env->amask; @@ -2941,7 +2943,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct= TranslationBlock *tb) ctx.ir =3D cpu_std_ir; #else ctx.palbr =3D env->palbr; - ctx.ir =3D (tb->flags & TB_FLAGS_PAL_MODE ? cpu_pal_ir : cpu_std_ir); + ctx.ir =3D (ctx.tbflags & TB_FLAGS_PAL_MODE ? cpu_pal_ir : cpu_std_ir); #endif =20 /* ??? Every TB begins with unset rounding mode, to be initialized on --=20 2.9.4 From nobody Sun Apr 28 21:11:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499991644016879.7416746410961; Thu, 13 Jul 2017 17:20:44 -0700 (PDT) Received: from localhost ([::1]:34766 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dVoLa-0005AU-8B for importer@patchew.org; Thu, 13 Jul 2017 20:20:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43210) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dVoJg-0003G5-VG for qemu-devel@nongnu.org; Thu, 13 Jul 2017 20:18:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dVoJc-00007h-LY for qemu-devel@nongnu.org; Thu, 13 Jul 2017 20:18:44 -0400 Received: from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:35013) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dVoJc-00007Y-Fc for qemu-devel@nongnu.org; Thu, 13 Jul 2017 20:18:40 -0400 Received: by mail-qk0-x243.google.com with SMTP id c18so129289qkb.2 for ; Thu, 13 Jul 2017 17:18:40 -0700 (PDT) Received: from bigtime.twiddle.net.com (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id v47sm5647206qtb.11.2017.07.13.17.18.37 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jul 2017 17:18:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=dcKesjHI/XRmxIdd/osoER/uWn++Ew0kGP3yOFa/sRE=; b=YSlOZSeJNFXM8imNEP8VqQ13Aj+kAtajqJxO9HUNlqT1CsjFUt/vL6Febw7ai+Tjw6 nrczylSPLMUiEDjYSKiA4pD9w33EMjKaFDiZlYc6+ScZgZxsd9acNuC4Wtc/45u7V+KW cf9VkEajIgntfgeFc3L2/tL1crH6q2Ci4g50SP6Zs5r8K6cShyTemutzIA1+0Sun3YE1 K21GZ1KqExln5h2MlSnxxUr+l8/0lfz3BQwxVTFJ710Ngyvf5rgji7Rk2TAHBYTK3G44 5lSq0V4AQwG2oDn6QtHBgs+YS6oHHXdzIXQhrAAKqwAuYcMCpRyPstRZ3KREwP6CtqRT I9RA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=dcKesjHI/XRmxIdd/osoER/uWn++Ew0kGP3yOFa/sRE=; b=hncAuLBahnKo51dFSz/doZv6TB4O9ZIapAzY4o7c8pO0NRfR7UfmoKm5d2Xp/Yg+nu s+KFD/x820jn+aA3ycKSeznQ9MPb04XWBVhZmkowgwSnWh18Gd9SAgL8pb015na5x3ry id46sI8PgxcXwDLIaHL+rNMUHH3dHB2KG3OFCXe2DBoUn3I/OQrxBqcGIyQc1cZJze+M hFIVJs4+otfGxHIEdbG16pAC7v7TRBzZJE9zE6N8WjyjMh6FGnvR61xVDtnsDVMBRpKd tdPLrMROIRYL2qVnRGp9p5FfjdQuIpqS0Y4vjEBOVb9c+JRBIXDzyGyXl4QGnuhrbZDh 26WA== X-Gm-Message-State: AIVw113ERuCTpVaK6Jb3Vt6uJkBxfcxMqX3qYtQYropcEvUgR9Gq/eRw +N7B6Rt7646NmWWA9cU= X-Received: by 10.55.86.5 with SMTP id k5mr7634606qkb.70.1499991519436; Thu, 13 Jul 2017 17:18:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Jul 2017 14:18:14 -1000 Message-Id: <20170714001819.1660-4-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170714001819.1660-1-rth@twiddle.net> References: <20170714001819.1660-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH 3/8] target/alpha: Merge several flag bytes into ENV->FLAGS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The flags are arranged such that we can manipulate them either a whole, or as individual bytes. The computation within cpu_get_tb_cpu_state is now reduced to a single load and mask. Signed-off-by: Richard Henderson Tested-by: Emilio G. Cota --- target/alpha/cpu.h | 70 +++++++++++++++++-------------------- hw/alpha/dp264.c | 1 - linux-user/main.c | 25 +++++++------ target/alpha/cpu.c | 7 ++-- target/alpha/helper.c | 12 +++---- target/alpha/machine.c | 10 ++---- target/alpha/translate.c | 91 +++++++++++++++++++++++++++++++-------------= ---- 7 files changed, 117 insertions(+), 99 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index aa83417..e95be2b 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -242,13 +242,11 @@ struct CPUAlphaState { uint8_t fpcr_dyn_round; uint8_t fpcr_flush_to_zero; =20 - /* The Internal Processor Registers. Some of these we assume always - exist for use in user-mode. */ - uint8_t ps; - uint8_t intr_flag; - uint8_t pal_mode; - uint8_t fen; + /* Mask of PALmode, Processor State et al. Most of this gets copied + into the TranslatorBlock flags and controls code generation. */ + uint32_t flags; =20 + /* The high 32-bits of the processor cycle counter. */ uint32_t pcc_ofs; =20 /* These pass data from the exception logic in the translator and @@ -398,24 +396,37 @@ enum { }; =20 /* Processor status constants. */ -enum { - /* Low 3 bits are interrupt mask level. */ - PS_INT_MASK =3D 7, +/* Low 3 bits are interrupt mask level. */ +#define PS_INT_MASK 7u =20 - /* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes; - The Unix PALcode only uses bit 4. */ - PS_USER_MODE =3D 8 -}; +/* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes; + The Unix PALcode only uses bit 4. */ +#define PS_USER_MODE 8u + +/* CPUAlphaState->flags constants. These are layed out so that we + can set or reset the pieces individually by assigning to the byte, + or manipulated as a whole. */ + +#define ENV_FLAG_PAL_SHIFT 0 +#define ENV_FLAG_PS_SHIFT 8 +#define ENV_FLAG_RX_SHIFT 16 +#define ENV_FLAG_FEN_SHIFT 24 + +#define ENV_FLAG_PAL_MODE (1u << ENV_FLAG_PAL_SHIFT) +#define ENV_FLAG_PS_USER (PS_USER_MODE << ENV_FLAG_PS_SHIFT) +#define ENV_FLAG_RX_FLAG (1u << ENV_FLAG_RX_SHIFT) +#define ENV_FLAG_FEN (1u << ENV_FLAG_FEN_SHIFT) + +#define ENV_FLAG_TB_MASK \ + (ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN) =20 static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) { - if (env->pal_mode) { - return MMU_KERNEL_IDX; - } else if (env->ps & PS_USER_MODE) { - return MMU_USER_IDX; - } else { - return MMU_KERNEL_IDX; + int ret =3D env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_= IDX; + if (env->flags & ENV_FLAG_PAL_MODE) { + ret =3D MMU_KERNEL_IDX; } + return ret; } =20 enum { @@ -482,31 +493,12 @@ QEMU_NORETURN void alpha_cpu_unassigned_access(CPUSta= te *cpu, hwaddr addr, int unused, unsigned size); #endif =20 -/* Bits in TB->FLAGS that control how translation is processed. */ -enum { - TB_FLAGS_PAL_MODE =3D 1, - TB_FLAGS_FEN =3D 2, - TB_FLAGS_USER_MODE =3D 8, -}; - static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *= pc, target_ulong *cs_base, uint32_t *p= flags) { - int flags =3D 0; - *pc =3D env->pc; *cs_base =3D 0; - - if (env->pal_mode) { - flags =3D TB_FLAGS_PAL_MODE; - } else { - flags =3D env->ps & PS_USER_MODE; - } - if (env->fen) { - flags |=3D TB_FLAGS_FEN; - } - - *pflags =3D flags; + *pflags =3D env->flags & ENV_FLAG_TB_MASK; } =20 #endif /* ALPHA_CPU_H */ diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c index 85405da..3b307ad 100644 --- a/hw/alpha/dp264.c +++ b/hw/alpha/dp264.c @@ -123,7 +123,6 @@ static void clipper_init(MachineState *machine) =20 /* Start all cpus at the PALcode RESET entry point. */ for (i =3D 0; i < smp_cpus; ++i) { - cpus[i]->env.pal_mode =3D 1; cpus[i]->env.pc =3D palcode_entry; cpus[i]->env.palbr =3D palcode_entry; } diff --git a/linux-user/main.c b/linux-user/main.c index ad03c9e..2b38d39 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3037,16 +3037,13 @@ void cpu_loop(CPUAlphaState *env) abi_long sysret; =20 while (1) { + bool arch_interrupt =3D true; + cpu_exec_start(cs); trapnr =3D cpu_exec(cs); cpu_exec_end(cs); process_queued_cpu_work(cs); =20 - /* All of the traps imply a transition through PALcode, which - implies an REI instruction has been executed. Which means - that the intr_flag should be cleared. */ - env->intr_flag =3D 0; - switch (trapnr) { case EXCP_RESET: fprintf(stderr, "Reset requested. Exit\n"); @@ -3063,7 +3060,6 @@ void cpu_loop(CPUAlphaState *env) exit(EXIT_FAILURE); break; case EXCP_MMFAULT: - env->lock_addr =3D -1; info.si_signo =3D TARGET_SIGSEGV; info.si_errno =3D 0; info.si_code =3D (page_get_flags(env->trap_arg0) & PAGE_VALID @@ -3072,7 +3068,6 @@ void cpu_loop(CPUAlphaState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_UNALIGN: - env->lock_addr =3D -1; info.si_signo =3D TARGET_SIGBUS; info.si_errno =3D 0; info.si_code =3D TARGET_BUS_ADRALN; @@ -3081,7 +3076,6 @@ void cpu_loop(CPUAlphaState *env) break; case EXCP_OPCDEC: do_sigill: - env->lock_addr =3D -1; info.si_signo =3D TARGET_SIGILL; info.si_errno =3D 0; info.si_code =3D TARGET_ILL_ILLOPC; @@ -3089,7 +3083,6 @@ void cpu_loop(CPUAlphaState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_ARITH: - env->lock_addr =3D -1; info.si_signo =3D TARGET_SIGFPE; info.si_errno =3D 0; info.si_code =3D TARGET_FPE_FLTINV; @@ -3100,7 +3093,6 @@ void cpu_loop(CPUAlphaState *env) /* No-op. Linux simply re-enables the FPU. */ break; case EXCP_CALL_PAL: - env->lock_addr =3D -1; switch (env->error_code) { case 0x80: /* BPT */ @@ -3197,10 +3189,11 @@ void cpu_loop(CPUAlphaState *env) case EXCP_DEBUG: info.si_signo =3D gdb_handlesig(cs, TARGET_SIGTRAP); if (info.si_signo) { - env->lock_addr =3D -1; info.si_errno =3D 0; info.si_code =3D TARGET_TRAP_BRKPT; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } else { + arch_interrupt =3D false; } break; case EXCP_INTERRUPT: @@ -3208,6 +3201,7 @@ void cpu_loop(CPUAlphaState *env) break; case EXCP_ATOMIC: cpu_exec_step_atomic(cs); + arch_interrupt =3D false; break; default: printf ("Unhandled trap: 0x%x\n", trapnr); @@ -3215,6 +3209,15 @@ void cpu_loop(CPUAlphaState *env) exit(EXIT_FAILURE); } process_pending_signals (env); + + /* Most of the traps imply a transition through PALcode, which + implies an REI instruction has been executed. Which means + that RX and LOCK_ADDR should be cleared. But there are a + few exceptions for traps internal to QEMU. */ + if (arch_interrupt) { + env->flags &=3D ~ENV_FLAG_RX_FLAG; + env->lock_addr =3D -1; + } } } #endif /* TARGET_ALPHA */ diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 8186c9d..76150f4 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -276,14 +276,15 @@ static void alpha_cpu_initfn(Object *obj) =20 alpha_translate_init(); =20 + env->lock_addr =3D -1; #if defined(CONFIG_USER_ONLY) - env->ps =3D PS_USER_MODE; + env->flags =3D ENV_FLAG_PS_USER | ENV_FLAG_FEN; cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD | FPCR_UNFD | FPCR_INED | FPCR_DNOD | FPCR_DYN_NORMAL)); +#else + env->flags =3D ENV_FLAG_PAL_MODE | ENV_FLAG_FEN; #endif - env->lock_addr =3D -1; - env->fen =3D 1; } =20 static void alpha_cpu_class_init(ObjectClass *oc, void *data) diff --git a/target/alpha/helper.c b/target/alpha/helper.c index a5c3088..34121f4 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -81,7 +81,7 @@ void helper_store_fpcr(CPUAlphaState *env, uint64_t val) static uint64_t *cpu_alpha_addr_gr(CPUAlphaState *env, unsigned reg) { #ifndef CONFIG_USER_ONLY - if (env->pal_mode) { + if (env->flags & ENV_FLAG_PAL_MODE) { if (reg >=3D 8 && reg <=3D 14) { return &env->shadow[reg - 8]; } else if (reg =3D=3D 25) { @@ -364,13 +364,13 @@ void alpha_cpu_do_interrupt(CPUState *cs) =20 /* Remember where the exception happened. Emulate real hardware in that the low bit of the PC indicates PALmode. */ - env->exc_addr =3D env->pc | env->pal_mode; + env->exc_addr =3D env->pc | (env->flags & ENV_FLAG_PAL_MODE); =20 /* Continue execution at the PALcode entry point. */ env->pc =3D env->palbr + i; =20 /* Switch to PALmode. */ - env->pal_mode =3D 1; + env->flags |=3D ENV_FLAG_PAL_MODE; #endif /* !USER_ONLY */ } =20 @@ -381,14 +381,14 @@ bool alpha_cpu_exec_interrupt(CPUState *cs, int inter= rupt_request) int idx =3D -1; =20 /* We never take interrupts while in PALmode. */ - if (env->pal_mode) { + if (env->flags & ENV_FLAG_PAL_MODE) { return false; } =20 /* Fall through the switch, collecting the highest priority interrupt that isn't masked by the processor status IPL. */ /* ??? This hard-codes the OSF/1 interrupt levels. */ - switch (env->ps & PS_INT_MASK) { + switch ((env->flags >> ENV_FLAG_PS_SHIFT) & PS_INT_MASK) { case 0 ... 3: if (interrupt_request & CPU_INTERRUPT_HARD) { idx =3D EXCP_DEV_INTERRUPT; @@ -432,7 +432,7 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprint= f_function cpu_fprintf, int i; =20 cpu_fprintf(f, " PC " TARGET_FMT_lx " PS %02x\n", - env->pc, env->ps); + env->pc, extract32(env->flags, ENV_FLAG_PS_SHIFT, 8)); for (i =3D 0; i < 31; i++) { cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx " ", i, linux_reg_names[i], cpu_alpha_load_gr(env, i)); diff --git a/target/alpha/machine.c b/target/alpha/machine.c index a102645..0914ba5 100644 --- a/target/alpha/machine.c +++ b/target/alpha/machine.c @@ -48,11 +48,7 @@ static VMStateField vmstate_env_fields[] =3D { VMSTATE_UINTTL(lock_addr, CPUAlphaState), VMSTATE_UINTTL(lock_value, CPUAlphaState), =20 - VMSTATE_UINT8(ps, CPUAlphaState), - VMSTATE_UINT8(intr_flag, CPUAlphaState), - VMSTATE_UINT8(pal_mode, CPUAlphaState), - VMSTATE_UINT8(fen, CPUAlphaState), - + VMSTATE_UINT32(flags, CPUAlphaState), VMSTATE_UINT32(pcc_ofs, CPUAlphaState), =20 VMSTATE_UINTTL(trap_arg0, CPUAlphaState), @@ -74,8 +70,8 @@ static VMStateField vmstate_env_fields[] =3D { =20 static const VMStateDescription vmstate_env =3D { .name =3D "env", - .version_id =3D 2, - .minimum_version_id =3D 2, + .version_id =3D 3, + .minimum_version_id =3D 3, .fields =3D vmstate_env_fields, }; =20 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 48be19a..140d6f3 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -269,6 +269,27 @@ static TCGv dest_fpr(DisasContext *ctx, unsigned reg) } } =20 +static int get_flag_ofs(unsigned shift) +{ + int ofs =3D offsetof(CPUAlphaState, flags); +#ifdef HOST_WORDS_BIGENDIAN + ofs +=3D 3 - (shift / 8); +#else + ofs +=3D shift / 8; +#endif + return ofs; +} + +static void ld_flag_byte(TCGv val, unsigned shift) +{ + tcg_gen_ld8u_i64(val, cpu_env, get_flag_ofs(shift)); +} + +static void st_flag_byte(TCGv val, unsigned shift) +{ + tcg_gen_st8_i64(val, cpu_env, get_flag_ofs(shift)); +} + static void gen_excp_1(int exception, int error_code) { TCGv_i32 tmp1, tmp2; @@ -453,7 +474,7 @@ static ExitStatus gen_store_conditional(DisasContext *c= tx, int ra, int rb, static bool in_superpage(DisasContext *ctx, int64_t addr) { #ifndef CONFIG_USER_ONLY - return ((ctx->tbflags & TB_FLAGS_USER_MODE) =3D=3D 0 + return ((ctx->tbflags & ENV_FLAG_PS_USER) =3D=3D 0 && addr >> TARGET_VIRT_ADDR_SPACE_BITS =3D=3D -1 && ((addr >> 41) & 3) =3D=3D 2); #else @@ -1125,16 +1146,15 @@ static void gen_msk_l(DisasContext *ctx, TCGv vc, T= CGv va, int rb, bool islit, =20 static void gen_rx(DisasContext *ctx, int ra, int set) { - TCGv_i32 tmp; + TCGv tmp; =20 if (ra !=3D 31) { - tcg_gen_ld8u_i64(ctx->ir[ra], cpu_env, - offsetof(CPUAlphaState, intr_flag)); + ld_flag_byte(ctx->ir[ra], ENV_FLAG_RX_SHIFT); } =20 - tmp =3D tcg_const_i32(set); - tcg_gen_st8_i32(tmp, cpu_env, offsetof(CPUAlphaState, intr_flag)); - tcg_temp_free_i32(tmp); + tmp =3D tcg_const_i64(set); + st_flag_byte(ctx->ir[ra], ENV_FLAG_RX_SHIFT); + tcg_temp_free(tmp); } =20 static ExitStatus gen_call_pal(DisasContext *ctx, int palcode) @@ -1168,7 +1188,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int= palcode) =20 #ifndef CONFIG_USER_ONLY /* Privileged PAL code */ - if (palcode < 0x40 && (ctx->tbflags & TB_FLAGS_USER_MODE) =3D=3D 0) { + if (palcode < 0x40 && (ctx->tbflags & ENV_FLAG_PS_USER) =3D=3D 0) { TCGv tmp; switch (palcode) { case 0x01: @@ -1199,13 +1219,12 @@ static ExitStatus gen_call_pal(DisasContext *ctx, i= nt palcode) /* SWPIPL */ /* Note that we already know we're in kernel mode, so we know that PS only contains the 3 IPL bits. */ - tcg_gen_ld8u_i64(ctx->ir[IR_V0], cpu_env, - offsetof(CPUAlphaState, ps)); + ld_flag_byte(ctx->ir[IR_V0], ENV_FLAG_PS_SHIFT); =20 /* But make sure and store only the 3 IPL bits from the user. = */ tmp =3D tcg_temp_new(); tcg_gen_andi_i64(tmp, ctx->ir[IR_A0], PS_INT_MASK); - tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, ps)); + st_flag_byte(tmp, ENV_FLAG_PS_SHIFT); tcg_temp_free(tmp); =20 /* Allow interrupts to be recognized right away. */ @@ -1214,9 +1233,9 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int= palcode) =20 case 0x36: /* RDPS */ - tcg_gen_ld8u_i64(ctx->ir[IR_V0], cpu_env, - offsetof(CPUAlphaState, ps)); + ld_flag_byte(ctx->ir[IR_V0], ENV_FLAG_PS_SHIFT); break; + case 0x38: /* WRUSP */ tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env, @@ -1259,11 +1278,11 @@ static ExitStatus gen_call_pal(DisasContext *ctx, i= nt palcode) uint64_t exc_addr =3D ctx->pc; uint64_t entry =3D ctx->palbr; =20 - if (ctx->tbflags & TB_FLAGS_PAL_MODE) { + if (ctx->tbflags & ENV_FLAG_PAL_MODE) { exc_addr |=3D 1; } else { tcg_gen_movi_i64(tmp, 1); - tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, pal_mode= )); + st_flag_byte(tmp, ENV_FLAG_PAL_SHIFT); } =20 tcg_gen_movi_i64(tmp, exc_addr); @@ -1293,14 +1312,11 @@ static ExitStatus gen_call_pal(DisasContext *ctx, i= nt palcode) =20 #ifndef CONFIG_USER_ONLY =20 -#define PR_BYTE 0x100000 #define PR_LONG 0x200000 =20 static int cpu_pr_data(int pr) { switch (pr) { - case 0: return offsetof(CPUAlphaState, ps) | PR_BYTE; - case 1: return offsetof(CPUAlphaState, fen) | PR_BYTE; case 2: return offsetof(CPUAlphaState, pcc_ofs) | PR_LONG; case 3: return offsetof(CPUAlphaState, trap_arg0); case 4: return offsetof(CPUAlphaState, trap_arg1); @@ -1350,14 +1366,19 @@ static ExitStatus gen_mfpr(DisasContext *ctx, TCGv = va, int regno) } break; =20 + case 0: /* PS */ + ld_flag_byte(va, ENV_FLAG_PS_SHIFT); + break; + case 1: /* FEN */ + ld_flag_byte(va, ENV_FLAG_FEN_SHIFT); + break; + default: /* The basic registers are data only, and unknown registers are read-zero, write-ignore. */ data =3D cpu_pr_data(regno); if (data =3D=3D 0) { tcg_gen_movi_i64(va, 0); - } else if (data & PR_BYTE) { - tcg_gen_ld8u_i64(va, cpu_env, data & ~PR_BYTE); } else if (data & PR_LONG) { tcg_gen_ld32s_i64(va, cpu_env, data & ~PR_LONG); } else { @@ -1417,14 +1438,19 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv = vb, int regno) tcg_gen_mov_i64(cpu_std_ir[regno], vb); break; =20 + case 0: /* PS */ + st_flag_byte(vb, ENV_FLAG_PS_SHIFT); + break; + case 1: /* FEN */ + st_flag_byte(vb, ENV_FLAG_FEN_SHIFT); + break; + default: /* The basic registers are data only, and unknown registers are read-zero, write-ignore. */ data =3D cpu_pr_data(regno); if (data !=3D 0) { - if (data & PR_BYTE) { - tcg_gen_st8_i64(vb, cpu_env, data & ~PR_BYTE); - } else if (data & PR_LONG) { + if (data & PR_LONG) { tcg_gen_st32_i64(vb, cpu_env, data & ~PR_LONG); } else { tcg_gen_st_i64(vb, cpu_env, data); @@ -2430,7 +2456,7 @@ static ExitStatus translate_one(DisasContext *ctx, ui= nt32_t insn) case 0x19: /* HW_MFPR (PALcode) */ #ifndef CONFIG_USER_ONLY - REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE); + REQUIRE_TB_FLAG(ENV_FLAG_PAL_MODE); va =3D dest_gpr(ctx, ra); ret =3D gen_mfpr(ctx, va, insn & 0xffff); break; @@ -2452,7 +2478,7 @@ static ExitStatus translate_one(DisasContext *ctx, ui= nt32_t insn) case 0x1B: /* HW_LD (PALcode) */ #ifndef CONFIG_USER_ONLY - REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE); + REQUIRE_TB_FLAG(ENV_FLAG_PAL_MODE); { TCGv addr =3D tcg_temp_new(); vb =3D load_gpr(ctx, rb); @@ -2674,7 +2700,7 @@ static ExitStatus translate_one(DisasContext *ctx, ui= nt32_t insn) case 0x1D: /* HW_MTPR (PALcode) */ #ifndef CONFIG_USER_ONLY - REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE); + REQUIRE_TB_FLAG(ENV_FLAG_PAL_MODE); vb =3D load_gpr(ctx, rb); ret =3D gen_mtpr(ctx, vb, insn & 0xffff); break; @@ -2685,7 +2711,7 @@ static ExitStatus translate_one(DisasContext *ctx, ui= nt32_t insn) case 0x1E: /* HW_RET (PALcode) */ #ifndef CONFIG_USER_ONLY - REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE); + REQUIRE_TB_FLAG(ENV_FLAG_PAL_MODE); if (rb =3D=3D 31) { /* Pre-EV6 CPUs interpreted this as HW_REI, loading the return address from EXC_ADDR. This turns out to be useful for our @@ -2695,12 +2721,13 @@ static ExitStatus translate_one(DisasContext *ctx, = uint32_t insn) } else { vb =3D load_gpr(ctx, rb); } + tcg_gen_movi_i64(cpu_lock_addr, -1); tmp =3D tcg_temp_new(); tcg_gen_movi_i64(tmp, 0); - tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, intr_flag)); - tcg_gen_movi_i64(cpu_lock_addr, -1); + st_flag_byte(tmp, ENV_FLAG_RX_SHIFT); tcg_gen_andi_i64(tmp, vb, 1); - tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, pal_mode)); + st_flag_byte(tmp, ENV_FLAG_PAL_SHIFT); + tcg_temp_free(tmp); tcg_gen_andi_i64(cpu_pc, vb, ~3); /* Allow interrupts to be recognized right away. */ ret =3D EXIT_PC_UPDATED_NOCHAIN; @@ -2712,7 +2739,7 @@ static ExitStatus translate_one(DisasContext *ctx, ui= nt32_t insn) case 0x1F: /* HW_ST (PALcode) */ #ifndef CONFIG_USER_ONLY - REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE); + REQUIRE_TB_FLAG(ENV_FLAG_PAL_MODE); { switch ((insn >> 12) & 0xF) { case 0x0: @@ -2943,7 +2970,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct= TranslationBlock *tb) ctx.ir =3D cpu_std_ir; #else ctx.palbr =3D env->palbr; - ctx.ir =3D (ctx.tbflags & TB_FLAGS_PAL_MODE ? cpu_pal_ir : cpu_std_ir); + ctx.ir =3D (ctx.tbflags & ENV_FLAG_PAL_MODE ? cpu_pal_ir : cpu_std_ir); #endif =20 /* ??? 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X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-devel] [PATCH 4/8] target/alpha: Fix temp leak in gen_bcond X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Tested-by: Emilio G. Cota --- target/alpha/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 140d6f3..d684a7b 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -565,16 +565,16 @@ static ExitStatus gen_bcond_internal(DisasContext *ct= x, TCGCond cond, static ExitStatus gen_bcond(DisasContext *ctx, TCGCond cond, int ra, int32_t disp, int mask) { - TCGv cmp_tmp; - if (mask) { - cmp_tmp =3D tcg_temp_new(); - tcg_gen_andi_i64(cmp_tmp, load_gpr(ctx, ra), 1); - } else { - cmp_tmp =3D load_gpr(ctx, ra); - } + TCGv tmp =3D tcg_temp_new(); + ExitStatus ret; =20 - return gen_bcond_internal(ctx, cond, cmp_tmp, disp); + tcg_gen_andi_i64(tmp, load_gpr(ctx, ra), 1); + ret =3D gen_bcond_internal(ctx, cond, tmp, disp); + tcg_temp_free(tmp); + return ret; + } + return gen_bcond_internal(ctx, cond, load_gpr(ctx, ra), disp); } =20 /* Fold -0.0 for comparison with COND. */ --=20 2.9.4 From nobody Sun Apr 28 21:11:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499991845554126.2885959092464; Thu, 13 Jul 2017 17:24:05 -0700 (PDT) Received: from localhost ([::1]:34776 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dVoOq-00009J-C0 for importer@patchew.org; Thu, 13 Jul 2017 20:24:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43204) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dVoJg-0003Fb-5l for qemu-devel@nongnu.org; Thu, 13 Jul 2017 20:18:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dVoJf-00008s-EQ for qemu-devel@nongnu.org; Thu, 13 Jul 2017 20:18:44 -0400 Received: from mail-qk0-x244.google.com ([2607:f8b0:400d:c09::244]:35015) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dVoJf-00008h-9n for qemu-devel@nongnu.org; Thu, 13 Jul 2017 20:18:43 -0400 Received: by mail-qk0-x244.google.com with SMTP id c18so129381qkb.2 for ; Thu, 13 Jul 2017 17:18:43 -0700 (PDT) Received: from bigtime.twiddle.net.com (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id v47sm5647206qtb.11.2017.07.13.17.18.41 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jul 2017 17:18:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=2J7mRMvXWppZlOIW/K6qn++52emjURixaLROWle0Zq8=; b=qT5Q/iAmuNmjVzLF+3u11HOh8f6Q/2op62rBns+tpyc6s9YrDGhuFPVHkwqRY7qrei 2FmUweXjjOkiM72ehNCfs131X9hYbmAg1gC4WQVF7/pGXJBoQGuJJCgJq9hbmh19xKU5 Tmg2KmR0b70j7B0U0/0e8KHnuzsGj1a7BT1j1dfnJWtbVBsLtZyclE3khlUN6G5WIWpH KHDVfU3ad2HHEbXP3JFUTqOKu/0qyR0vo7QkQYEUEu/JIvElzyz+pFbvp3sjCMRxwmi2 JkBa9yGjyoszLJsp/Q7ez8SXuV7QTEIwr491GPi2hXbE7I+lm4hyDq+q50zZVy1DAQNW +DTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=2J7mRMvXWppZlOIW/K6qn++52emjURixaLROWle0Zq8=; b=EA03cAOvK/U5umwwkoupruMHPaxKruEM+aQfpwB5iiVVQQIMYx7TuOWkyEcaAXqxwq qDBypGtjqWvZyKEIhlae+OnVGQPizN1Ya7OoCc8cyT1ltph97/jwGikY+usNl0vmTomE 3mV0apzQlss4US672mCDe2T7Z31Urm8UrzEPaZ4gI9skJQzkzAAsx/m014sAQlUylmBg lGKNKfJuW7zBBRlpVQcxmLZhDOvnZtSlVXZ0JbCfAwLCUkfbRitZAq5DrA7+AjR7yGj2 dFaJlWvkV2XxefWPdTSAY4P3wYHWwOJXXpXfFJh8P4oTikD5tqoeO2rnz+IhanvWz6k7 svhA== X-Gm-Message-State: AIVw112SQkzaWoJFzBxI175rJtLJtNYZdwmV5MavGyFbc6Ki6eON49qs d6bXSsDOoGMZoEKROCM= X-Received: by 10.55.175.3 with SMTP id y3mr7802110qke.185.1499991522676; Thu, 13 Jul 2017 17:18:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Jul 2017 14:18:16 -1000 Message-Id: <20170714001819.1660-6-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170714001819.1660-1-rth@twiddle.net> References: <20170714001819.1660-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-devel] [PATCH 5/8] target/alpha: Fix temp leak in gen_mtpr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Tested-by: Emilio G. Cota --- target/alpha/translate.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index d684a7b..5e37b1a 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -1392,7 +1392,6 @@ static ExitStatus gen_mfpr(DisasContext *ctx, TCGv va= , int regno) =20 static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb, int regno) { - TCGv tmp; int data; =20 switch (regno) { @@ -1408,9 +1407,12 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv v= b, int regno) =20 case 253: /* WAIT */ - tmp =3D tcg_const_i64(1); - tcg_gen_st32_i64(tmp, cpu_env, -offsetof(AlphaCPU, env) + - offsetof(CPUState, halted)); + { + TCGv_i32 tmp =3D tcg_const_i32(1); + tcg_gen_st_i32(tmp, cpu_env, -offsetof(AlphaCPU, env) + + offsetof(CPUState, halted)); + tcg_temp_free_i32(tmp); + } return gen_excp(ctx, EXCP_HALTED, 0); =20 case 252: --=20 2.9.4 From nobody Sun Apr 28 21:11:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149999176632181.16275087962379; Thu, 13 Jul 2017 17:22:46 -0700 (PDT) Received: from localhost ([::1]:34772 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dVoNZ-0006s4-2u for importer@patchew.org; Thu, 13 Jul 2017 20:22:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43230) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dVoJk-0003J9-7E for qemu-devel@nongnu.org; Thu, 13 Jul 2017 20:18:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dVoJh-00009U-1v for qemu-devel@nongnu.org; Thu, 13 Jul 2017 20:18:48 -0400 Received: from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:33568) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dVoJg-00009F-Tz for qemu-devel@nongnu.org; Thu, 13 Jul 2017 20:18:44 -0400 Received: by mail-qk0-x243.google.com with SMTP id a66so9259128qkb.0 for ; Thu, 13 Jul 2017 17:18:44 -0700 (PDT) Received: from bigtime.twiddle.net.com (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id v47sm5647206qtb.11.2017.07.13.17.18.42 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jul 2017 17:18:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=jZx9OxFQFgw/zbpVZRthrcso0ZrNZJa3h8FBH+q5FZ8=; b=POtPI9u+i6ekaGKFiBgO9QoQdjyEUNeeo3rXHxaf5+Wp3PFRH1rDbWOTR2w6XAiqux FvuOpsp95WuBF3/zoCmcTeVAMzBC2Y+6nUkHlJyna7unxJPzxwq9LYKhRb/RczS5sC0l 9BUK66X1ksJS6kfYKwY9BpP4UbwGAIp4iWDMW60bflYWPkwALUv8i7naAzUl3tgAcLae BVotyYyL32mTV3/jzlWxjMil41XLaV4JuhJfU3stUKbdxNcQUFckjNqP7gwaEeA4iS2E Hd2PlAfqY404WKGTQbrMU790eiQPACEmdvB7ywSjEmzJKx6tCg4rf3rRxSPradzKeEFo j0Pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=jZx9OxFQFgw/zbpVZRthrcso0ZrNZJa3h8FBH+q5FZ8=; b=uA0XEjdPxBfcQle15JgS5C6QkZcMLBd+zyjOiKFwVcxw755kPCITQsF+ApE7XFKpNB k5TQeahVLkXpp/ZUBNseuEC7qWkfqXLqm+Gg9UFmrppOOQWB6H46srWzKlMhpMnhu6jb bOkSiUoWQQBquocjkfs5InSqtUfShlm5odi/T0VgeKcLcxurySY+8/3qhN6lk4id7NNi Deh8ivJ1kIF0fBSWECxyzu90P5smRusPr/ry5m99HWx5JWOCjaaFf6SIJM1i/bk81tRl JXfXiCKCw1H2NnrJ/jVaVp2d2nGYs9bGN7kuEdfcceLr0+vWC6ycbgAZiMjHJEnT+byd IZ2Q== X-Gm-Message-State: AIVw110eisO9dgpi0Kesx/Cz6rYG9pQ1BCf6G6/CEAVPy0yoXxrlkBmJ eo2lFCzRfqLQuxkQQvQ= X-Received: by 10.55.54.196 with SMTP id d187mr7888177qka.96.1499991524295; Thu, 13 Jul 2017 17:18:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Jul 2017 14:18:17 -1000 Message-Id: <20170714001819.1660-7-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170714001819.1660-1-rth@twiddle.net> References: <20170714001819.1660-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH 6/8] target/alpha: Fix temp leak in gen_call_pal X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Tested-by: Emilio G. Cota --- target/alpha/translate.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 5e37b1a..326af7f 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -1189,7 +1189,6 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int= palcode) #ifndef CONFIG_USER_ONLY /* Privileged PAL code */ if (palcode < 0x40 && (ctx->tbflags & ENV_FLAG_PS_USER) =3D=3D 0) { - TCGv tmp; switch (palcode) { case 0x01: /* CFLUSH */ @@ -1222,10 +1221,12 @@ static ExitStatus gen_call_pal(DisasContext *ctx, i= nt palcode) ld_flag_byte(ctx->ir[IR_V0], ENV_FLAG_PS_SHIFT); =20 /* But make sure and store only the 3 IPL bits from the user. = */ - tmp =3D tcg_temp_new(); - tcg_gen_andi_i64(tmp, ctx->ir[IR_A0], PS_INT_MASK); - st_flag_byte(tmp, ENV_FLAG_PS_SHIFT); - tcg_temp_free(tmp); + { + TCGv tmp =3D tcg_temp_new(); + tcg_gen_andi_i64(tmp, ctx->ir[IR_A0], PS_INT_MASK); + st_flag_byte(tmp, ENV_FLAG_PS_SHIFT); + tcg_temp_free(tmp); + } =20 /* Allow interrupts to be recognized right away. */ tcg_gen_movi_i64(cpu_pc, ctx->pc); @@ -1254,9 +1255,12 @@ static ExitStatus gen_call_pal(DisasContext *ctx, in= t palcode) =20 case 0x3E: /* WTINT */ - tmp =3D tcg_const_i64(1); - tcg_gen_st32_i64(tmp, cpu_env, -offsetof(AlphaCPU, env) + - offsetof(CPUState, halted)); + { + TCGv_i32 tmp =3D tcg_const_i32(1); + tcg_gen_st_i32(tmp, cpu_env, -offsetof(AlphaCPU, env) + + offsetof(CPUState, halted)); + tcg_temp_free_i32(tmp); + } tcg_gen_movi_i64(ctx->ir[IR_V0], 0); return gen_excp(ctx, EXCP_HALTED, 0); =20 --=20 2.9.4 From nobody Sun Apr 28 21:11:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499991640258928.2086234770493; Thu, 13 Jul 2017 17:20:40 -0700 (PDT) Received: from localhost ([::1]:34765 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dVoLX-00058R-3W for importer@patchew.org; Thu, 13 Jul 2017 20:20:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43231) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dVoJk-0003JA-7I for qemu-devel@nongnu.org; Thu, 13 Jul 2017 20:18:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dVoJi-0000A0-Nt for qemu-devel@nongnu.org; Thu, 13 Jul 2017 20:18:48 -0400 Received: from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:33569) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dVoJi-00009v-JZ for qemu-devel@nongnu.org; Thu, 13 Jul 2017 20:18:46 -0400 Received: by mail-qk0-x243.google.com with SMTP id a66so9259162qkb.0 for ; Thu, 13 Jul 2017 17:18:46 -0700 (PDT) Received: from bigtime.twiddle.net.com (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id v47sm5647206qtb.11.2017.07.13.17.18.44 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jul 2017 17:18:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=ZmHuiWoakY8zNnYH6XmHs8ZiM+9YjeVIieVCPc/utj4=; b=mk3ZvJq5lz48BnfMNCC9vZZtEgTqvrwyFoVq1fD78g6914tua6WCjbf4PAj+LBDo3O 0/xz9nfa95r0Tg6x18xq0FOqfwFKTXdhf+gXu+flpTPbLtRuNjVMT49ld6420dhLXnSt R9L+gvSlX4aGzUNppdL64vUTN7ZJChtPKQL75pcQ75TTlzv96loDrDOr+DmhlX9B75+E 9cu2mxNIKjgYbJMvKiemQypn+x/8wRDDLMpfGOuo3wX0bR5n3rz+vdbzvIJVUGrxOTkt cJWu8gkB2WSvyVIyIpWHf4BG03PoKXY7DpCIv5vyTPE4EKUG25yaqwCDq9p5ZxHbqa87 /mcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=ZmHuiWoakY8zNnYH6XmHs8ZiM+9YjeVIieVCPc/utj4=; b=i6+AFyXjbCFkhaITSFJ8m4G2JvIY2Yl0/k+pdbnIJ78wcEDsB1A8KKzsb7u0maoW3v sKj8knmUYk1U5w+/zzDiJp7uxTQWak6L1UO9nTXW6BVXGCiQU18rneVvFGsHOMHw/AkO E2pNVRfxg9IamBifF2DHoi+yvfn8crdTmvYNCp1wiziZW+JG1qel3zaVws4sVVdUmH46 fk/Mgs4LllwiNgEhckxLF6AG+iKUyLwrgjVCwFwNr2JmGndGlaZrYINPlIOcVBWnyeZB ygnn8Fg1s2YiTG1W/VZGTn2efKY8IHPm2+WceVrsZcalhgrYpLTWCyUxxwkP7L6XNCzY jZqQ== X-Gm-Message-State: AIVw113B2qbVRbc07cBXPG2+z0tXxDCX1SA/GE8kUmmZ8MFd6gHqsdcK 5UFkl7piJCS31G/rBOA= X-Received: by 10.55.221.76 with SMTP id n73mr8714709qki.186.1499991525995; Thu, 13 Jul 2017 17:18:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Jul 2017 14:18:18 -1000 Message-Id: <20170714001819.1660-8-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170714001819.1660-1-rth@twiddle.net> References: <20170714001819.1660-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH 7/8] target/alpha: Fix temp leak in gen_fbcond X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Tested-by: Emilio G. Cota --- target/alpha/translate.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 326af7f..aaaf28f 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -613,8 +613,12 @@ static ExitStatus gen_fbcond(DisasContext *ctx, TCGCon= d cond, int ra, int32_t disp) { TCGv cmp_tmp =3D tcg_temp_new(); + ExitStatus ret; + gen_fold_mzero(cond, cmp_tmp, load_fpr(ctx, ra)); - return gen_bcond_internal(ctx, cond, cmp_tmp, disp); + ret =3D gen_bcond_internal(ctx, cond, cmp_tmp, disp); + tcg_temp_free(cmp_tmp); + return ret; } =20 static void gen_fcmov(DisasContext *ctx, TCGCond cond, int ra, int rb, int= rc) --=20 2.9.4 From nobody Sun Apr 28 21:11:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499991776977105.06373035050319; Thu, 13 Jul 2017 17:22:56 -0700 (PDT) Received: from localhost ([::1]:34773 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dVoNj-00072p-Pt for importer@patchew.org; Thu, 13 Jul 2017 20:22:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43247) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dVoJl-0003Jr-5X for qemu-devel@nongnu.org; Thu, 13 Jul 2017 20:18:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dVoJk-0000B4-Cl for qemu-devel@nongnu.org; Thu, 13 Jul 2017 20:18:49 -0400 Received: from mail-qk0-x242.google.com ([2607:f8b0:400d:c09::242]:34523) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dVoJk-0000Am-9r for qemu-devel@nongnu.org; Thu, 13 Jul 2017 20:18:48 -0400 Received: by mail-qk0-x242.google.com with SMTP id q66so10270870qki.1 for ; Thu, 13 Jul 2017 17:18:48 -0700 (PDT) Received: from bigtime.twiddle.net.com (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id v47sm5647206qtb.11.2017.07.13.17.18.46 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jul 2017 17:18:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=5tcUOzlhEu1ZK4YprJ+t+YJlQYHldAVPkxY1WeyBwbM=; b=KwFdsA8gxKmwMupN3YKqFsykVpM05FKhuug0jjtADhd3cgkqNyEv2UvdI8daY7y/8z dWV7Ti7wJmNh7hYCjae3SYbroX7VcrwvNitqf+7/zQ82ve83qVqa4Qdoc0gnTrRc2Ak1 Tl2nsaWAf+MSBLGKi49lyD703aAYEB0jOXSIeu0uTWoZV8v2r0Dcl24YmLUu4l3dys4C Ek2T0D+LHu8nKcyBpO5qLlQ9eJJbRziPl8ktUh0rMC1W7tq2cqdhIFK2YZaQWWNqxeEM f3vChackxsNSNsTu8mi4hREaTLZeM94QKGPE12m5HHX22zkOn8g73rsWLo9rxU9YBSfK NzFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=5tcUOzlhEu1ZK4YprJ+t+YJlQYHldAVPkxY1WeyBwbM=; b=aZI35up04UoytnaKFsAzhKNTLDLSRAjYeENalFos6Ge373KegA3qp69ojBIQuw16e4 vmnCAw1bIEWi96cu48fXcUuR2g09bcE8soVGC9tO8VyXYJFRlr0uEjZBSK2aGz+I8VF4 9rBvL8s7MYagBxvYarQep0zgxLv35bWB5TeduWAJo8mUBOVquHtqA2gfx3AE1NcW44On TJiRNJM7tdkBe6YuI2STO1E6vtejApA/vi8pefiTkikIU57qfgeyAr2u3l4pvL/C9+rm LNGu7u39HCJsWOTc0AHa7oXgsOc/1PkWc4vDGd3jVGAOytiFmzXk5+NWYYx4N9ppdrjP Tufg== X-Gm-Message-State: AIVw110AvggQo6E3XsUBn7WQfOqNTP5MF4HYD70Q3h7TpIFYjj1/ImOK DhawwUhmL7hZ0S3I8pE= X-Received: by 10.233.232.212 with SMTP id a203mr7601441qkg.261.1499991527590; Thu, 13 Jul 2017 17:18:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Jul 2017 14:18:19 -1000 Message-Id: <20170714001819.1660-9-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170714001819.1660-1-rth@twiddle.net> References: <20170714001819.1660-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::242 Subject: [Qemu-devel] [PATCH 8/8] target/alpha: Log temp leaks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Tested-by: Emilio G. Cota --- target/alpha/translate.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index aaaf28f..90e6d52 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -3013,6 +3013,8 @@ void gen_intermediate_code(CPUAlphaState *env, struct= TranslationBlock *tb) } =20 gen_tb_start(tb); + tcg_clear_temp_count(); + do { tcg_gen_insn_start(ctx.pc); num_insns++; @@ -3035,6 +3037,10 @@ void gen_intermediate_code(CPUAlphaState *env, struc= t TranslationBlock *tb) ret =3D translate_one(ctxp, insn); free_context_temps(ctxp); =20 + if (tcg_check_temp_count()) { + qemu_log("TCG temporary leak before "TARGET_FMT_lx"\n", ctx.pc= ); + } + /* If we reach a page boundary, are single stepping, or exhaust instruction count, stop generation. */ if (ret =3D=3D NO_EXIT --=20 2.9.4