From nobody Mon Apr 29 04:35:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499808257885499.4743624629971; Tue, 11 Jul 2017 14:24:17 -0700 (PDT) Received: from localhost ([::1]:48995 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dV2dk-0001a3-KE for importer@patchew.org; Tue, 11 Jul 2017 17:24:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50180) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dV2cC-0000H6-8e for qemu-devel@nongnu.org; Tue, 11 Jul 2017 17:22:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dV2c9-0005ts-46 for qemu-devel@nongnu.org; Tue, 11 Jul 2017 17:22:40 -0400 Received: from mail-qk0-f195.google.com ([209.85.220.195]:33687) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dV2c8-0005tO-Vf for qemu-devel@nongnu.org; Tue, 11 Jul 2017 17:22:37 -0400 Received: by mail-qk0-f195.google.com with SMTP id p21so682922qke.0 for ; Tue, 11 Jul 2017 14:22:36 -0700 (PDT) Received: from bigtime.twiddle.net.com (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id v17sm357973qtc.39.2017.07.11.14.21.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Jul 2017 14:21:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=dS0mset5edNCmbPxIx8UPJV/1DTqd7mzes8Fiw+TMlI=; b=ceOijue0KofT7kFbx0XndcBT7w2acEIaXiR8dqwryjV/Y53Y6NUbtCjmgof1XkWOuB THTivQ5I39L4brkC6lIWWihsjN9GoL+Mfzu+wIae364D8ccKH8tWmF7UvPYUwVnMzh+h xSEgHiS71WP0iz4ao/ktNcmQ3QB7HuggdYSY48C0cX1yBPQugiHf3nMyIeCUWzpT6WZ3 EQIS/qJAkKNl7KMsZLDiLy3/wP3RnWfhsZ/1czeenyWWWTWleCRcGpIqRezuw0CF4OLJ D8Ed9Ai5TuWgCJdo9glZD1ffgLUr/WFmh5iemio0RsJHP0m0EEUQQZen99n17yxgJCu+ +RNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=dS0mset5edNCmbPxIx8UPJV/1DTqd7mzes8Fiw+TMlI=; b=cfnwRJhxNNVGbQTIRP00naKR3jEqj5GDluDH/N0UQTwd0IGis+MDC/KEIq9gv+WotA TVYEOxZbS14edFMTNgn+XqDmwct0oUvt87vVba4147xLOFgth0DwXufD5+kGEOXyfzD/ lw8Oe/VugNL68FN8uLRsS52d0MgyKqxt5AECsI5rJtN74blAH4x57/16H8Mo+BmZ0Bwe 9y480N5DdkmgxQIa5EtzHJaa74BciNOhGbJLHfOBVrkf359zxSgHHZP7ZBkXCOFv45rg d+G21U8Fmv+fU1koiL42hneuRRWNPaZhXO73+9skYfJCWdDHchQCT6wdEXkV9MKFa52a Q+XQ== X-Gm-Message-State: AIVw1113FTyG3Ijk7ONcoazc8UAmr1oPij9orX9iAMWVzZ57DFvWrafU 4AVqQ0n86FwPsp3Dz8I= X-Received: by 10.55.167.1 with SMTP id q1mr2380989qke.223.1499808096027; Tue, 11 Jul 2017 14:21:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 11 Jul 2017 11:21:22 -1000 Message-Id: <20170711212123.4368-2-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170711212123.4368-1-rth@twiddle.net> References: <20170711212123.4368-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.195 Subject: [Qemu-devel] [PATCH 1/2] target/i386: Decode AMD XOP prefix X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, ehabkost@redhat.com, ricardo.ribalda@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/i386/translate.c | 46 ++++++++++++++++++++++++++++++++-------------- 1 file changed, 32 insertions(+), 14 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index ed3b896..6082db2 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -4500,8 +4500,9 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, #endif case 0xc5: /* 2-byte VEX */ case 0xc4: /* 3-byte VEX */ + case 0x8f: /* 3-byte XOP */ /* VEX prefixes cannot be used except in 32-bit mode. - Otherwise the instruction is LES or LDS. */ + Otherwise the instruction is LES, LDS, or POP. */ if (s->code32 && !s->vm86) { static const int pp_prefix[4] =3D { 0, PREFIX_DATA, PREFIX_REPZ, PREFIX_REPNZ @@ -4510,7 +4511,13 @@ static target_ulong disas_insn(CPUX86State *env, Dis= asContext *s, =20 if (!CODE64(s) && (vex2 & 0xc0) !=3D 0xc0) { /* 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b, - otherwise the instruction is LES or LDS. */ + otherwise the instruction is LES, LDS, or POP. */ + break; + } + if (b =3D=3D 0x8f && (vex2 & 0x1f) < 8) { + /* If the value of the XOP.map_select field is less than 8, + the first two bytes of the three-byte XOP are interpret= ed + as a form of the POP instruction. */ break; } s->pc++; @@ -4536,18 +4543,25 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, #endif vex3 =3D cpu_ldub_code(env, s->pc++); rex_w =3D (vex3 >> 7) & 1; - switch (vex2 & 0x1f) { - case 0x01: /* Implied 0f leading opcode bytes. */ - b =3D cpu_ldub_code(env, s->pc++) | 0x100; - break; - case 0x02: /* Implied 0f 38 leading opcode bytes. */ - b =3D 0x138; - break; - case 0x03: /* Implied 0f 3a leading opcode bytes. */ - b =3D 0x13a; - break; - default: /* Reserved for future use. */ - goto unknown_op; + if (b =3D=3D 0xc4) { + switch (vex2 & 0x1f) { + case 0x01: /* Implied 0f leading opcode bytes. */ + b =3D cpu_ldub_code(env, s->pc++) | 0x100; + break; + case 0x02: /* Implied 0f 38 leading opcode bytes. */ + b =3D 0x138; + break; + case 0x03: /* Implied 0f 3a leading opcode bytes. */ + b =3D 0x13a; + break; + default: /* Reserved for future use. */ + goto unknown_op; + } + } else { + /* Unlike VEX, XOP.map_select does not overlap the + base instruction set. Prepend the map_select to + the next opcode byte. */ + b =3D cpu_ldub_code(env, s->pc++) + (vex2 & 0x1f) * 0x= 100; } } s->vex_v =3D (~vex3 >> 3) & 0xf; @@ -8276,6 +8290,10 @@ static target_ulong disas_insn(CPUX86State *env, Dis= asContext *s, case 0x1d0 ... 0x1fe: gen_sse(env, s, b, pc_start, rex_r); break; + + case 0x800 ... 0x8ff: /* XOP opcode map 8 */ + case 0x900 ... 0x9ff: /* XOP opcode map 9 */ + case 0xa00 ... 0xaff: /* XOP opcode map 10 */ default: goto unknown_op; } --=20 2.9.4 From nobody Mon Apr 29 04:35:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499808186221422.6695927307152; Tue, 11 Jul 2017 14:23:06 -0700 (PDT) Received: from localhost ([::1]:48988 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dV2ca-0000ML-SI for importer@patchew.org; Tue, 11 Jul 2017 17:23:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49654) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dV2bF-0007rF-No for qemu-devel@nongnu.org; Tue, 11 Jul 2017 17:21:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dV2bE-0005FQ-4m for qemu-devel@nongnu.org; Tue, 11 Jul 2017 17:21:41 -0400 Received: from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:36717) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dV2bD-0005F8-Vo for qemu-devel@nongnu.org; Tue, 11 Jul 2017 17:21:40 -0400 Received: by mail-qk0-x243.google.com with SMTP id v143so660273qkb.3 for ; Tue, 11 Jul 2017 14:21:39 -0700 (PDT) Received: from bigtime.twiddle.net.com (rrcs-173-197-98-123.west.biz.rr.com. [173.197.98.123]) by smtp.gmail.com with ESMTPSA id v17sm357973qtc.39.2017.07.11.14.21.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Jul 2017 14:21:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=e56kfTrr5S4paIGdcHrn5rjenCccy/8oQWRecAn9zb8=; b=HC0KaSSwmwP95TN9xS9FOs63euUKGKYuTlAtPM4eihekAY62IrfelrfAD2IChUaORG xUa/XjAS4HVnbcVYLF0q8rI7E26HSlNnVXuYTMZCeoTxPn9vElRaZpq7T93iCw7gjh6g mobECi6tP1tqoGjmt8K3Dm8A1Z2KCHVHxiZAZuBNJaIMXSLsJualSy8F/PsysIWK6T8Q m8/GV9z0+57v7Rg42rRg2MRXufR9/z1wbAVYaD2N2g46hIw2lsk3T2kMqAk1s0RMeSh8 gFgIVk8kNrF4SQ+EANWaeNabWkE8svDtddHGUh9qc3Spo9SscwX1jRAtItO36TUTr3Eg jfMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=e56kfTrr5S4paIGdcHrn5rjenCccy/8oQWRecAn9zb8=; b=KiqiMnVJkTcC3Mk0o25eBNsM7iSpf2CCt6pm9OXq9i4S5brbXKheEj4AqrZhM9H+c/ Z3thiejA/V1Tw9AusAw3ph7tSaHfqRj28LXWR0kE6QtaG23Q53UZjcJJyvhbBWlEKOG+ DG6D1DMZzK9K+UZ8aeH8OOGAUKqSjakSGON9AqLZBdNeSA5cGBnVuNJTs9gI48BtdWft bUEvztQ8rACqrwI8UTVt44zPe/4vOUVbHg1TyMTQIBibQTdGQ+Ced7B5m6uhSVgOWL0U SRgNBRwWLELcd11RxSgPuhz8BPmjGWzLPH/uHHzxvvXzK9PEQpTVlZq4q9gz7EFccV/j iZcw== X-Gm-Message-State: AIVw111DDVcEXtZY2lP9CQYY/vb19fczeChCnT8WZdiKq6NUqWum53dy GmOcZFns8d39n1lIQcY= X-Received: by 10.55.190.134 with SMTP id o128mr2493049qkf.58.1499808099027; Tue, 11 Jul 2017 14:21:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 11 Jul 2017 11:21:23 -1000 Message-Id: <20170711212123.4368-3-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170711212123.4368-1-rth@twiddle.net> References: <20170711212123.4368-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH 2/2] target/i386: Implement all TBM instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, ehabkost@redhat.com, ricardo.ribalda@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reported-by: Ricardo Ribalda Delgado Signed-off-by: Richard Henderson --- target/i386/cc_helper_template.h | 18 ++++++ target/i386/cpu.h | 7 ++- target/i386/cc_helper.c | 28 +++++++-- target/i386/cpu.c | 3 +- target/i386/translate.c | 123 +++++++++++++++++++++++++++++++++++= +++- 5 files changed, 170 insertions(+), 9 deletions(-) diff --git a/target/i386/cc_helper_template.h b/target/i386/cc_helper_templ= ate.h index 607311f..6ce63b7 100644 --- a/target/i386/cc_helper_template.h +++ b/target/i386/cc_helper_template.h @@ -235,6 +235,24 @@ static int glue(compute_c_bmilg, SUFFIX)(DATA_TYPE dst= , DATA_TYPE src1) return src1 =3D=3D 0; } =20 +static int glue(compute_all_tbmadd, SUFFIX)(DATA_TYPE dst, DATA_TYPE src1) +{ + int cf, pf, af, zf, sf, of; + + cf =3D (src1 =3D=3D (DATA_TYPE)-1); + pf =3D 0; /* undefined */ + af =3D 0; /* undefined */ + zf =3D (dst =3D=3D 0) * CC_Z; + sf =3D lshift(dst, 8 - DATA_BITS) & CC_S; + of =3D 0; + return cf | pf | af | zf | sf | of; +} + +static int glue(compute_c_tbmadd, SUFFIX)(DATA_TYPE dst, DATA_TYPE src1) +{ + return src1 =3D=3D (DATA_TYPE)-1; +} + #undef DATA_BITS #undef SIGN_MASK #undef DATA_TYPE diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7a228af..537f592 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -774,11 +774,16 @@ typedef enum { CC_OP_SARL, CC_OP_SARQ, =20 - CC_OP_BMILGB, /* Z,S via CC_DST, C =3D SRC=3D=3D0; O=3D0; P,A undefine= d */ + CC_OP_BMILGB, /* Z,S via DST, C =3D SRC=3D=3D0; O=3D0; P,A undefined */ CC_OP_BMILGW, CC_OP_BMILGL, CC_OP_BMILGQ, =20 + CC_OP_TBMADDB, /* Z,S via DST; C =3D SRC=3D=3D-1; O=3D0; P,A undefined= */ + CC_OP_TBMADDW, + CC_OP_TBMADDL, + CC_OP_TBMADDQ, + CC_OP_ADCX, /* CC_DST =3D C, CC_SRC =3D rest. */ CC_OP_ADOX, /* CC_DST =3D O, CC_SRC =3D rest. */ CC_OP_ADCOX, /* CC_DST =3D C, CC_SRC2 =3D O, CC_SRC =3D rest. */ diff --git a/target/i386/cc_helper.c b/target/i386/cc_helper.c index c9c90e1..2f12c3b 100644 --- a/target/i386/cc_helper.c +++ b/target/i386/cc_helper.c @@ -98,9 +98,6 @@ target_ulong helper_cc_compute_all(target_ulong dst, targ= et_ulong src1, target_ulong src2, int op) { switch (op) { - default: /* should never happen */ - return 0; - case CC_OP_EFLAGS: return src1; case CC_OP_CLR: @@ -185,6 +182,13 @@ target_ulong helper_cc_compute_all(target_ulong dst, t= arget_ulong src1, case CC_OP_BMILGL: return compute_all_bmilgl(dst, src1); =20 + case CC_OP_TBMADDB: + return compute_all_tbmaddb(dst, src1); + case CC_OP_TBMADDW: + return compute_all_tbmaddw(dst, src1); + case CC_OP_TBMADDL: + return compute_all_tbmaddl(dst, src1); + case CC_OP_ADCX: return compute_all_adcx(dst, src1, src2); case CC_OP_ADOX: @@ -215,7 +219,12 @@ target_ulong helper_cc_compute_all(target_ulong dst, t= arget_ulong src1, return compute_all_sarq(dst, src1); case CC_OP_BMILGQ: return compute_all_bmilgq(dst, src1); + case CC_OP_TBMADDQ: + return compute_all_tbmaddq(dst, src1); #endif + + default: + g_assert_not_reached(); } } =20 @@ -228,7 +237,6 @@ target_ulong helper_cc_compute_c(target_ulong dst, targ= et_ulong src1, target_ulong src2, int op) { switch (op) { - default: /* should never happen */ case CC_OP_LOGICB: case CC_OP_LOGICW: case CC_OP_LOGICL: @@ -307,6 +315,13 @@ target_ulong helper_cc_compute_c(target_ulong dst, tar= get_ulong src1, case CC_OP_BMILGL: return compute_c_bmilgl(dst, src1); =20 + case CC_OP_TBMADDB: + return compute_c_tbmaddb(dst, src1); + case CC_OP_TBMADDW: + return compute_c_tbmaddw(dst, src1); + case CC_OP_TBMADDL: + return compute_c_tbmaddl(dst, src1); + #ifdef TARGET_X86_64 case CC_OP_ADDQ: return compute_c_addq(dst, src1); @@ -320,7 +335,12 @@ target_ulong helper_cc_compute_c(target_ulong dst, tar= get_ulong src1, return compute_c_shlq(dst, src1); case CC_OP_BMILGQ: return compute_c_bmilgq(dst, src1); + case CC_OP_TBMADDQ: + return compute_c_tbmaddq(dst, src1); #endif + + default: + g_assert_not_reached(); } } =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c571772..34ab828 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -227,7 +227,8 @@ static void x86_cpu_vendor_words2str(char *dst, uint32_= t vendor1, CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ TCG_EXT2_X86_64_FEATURES) #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ - CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) + CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ + CPUID_EXT3_TBM) #define TCG_EXT4_FEATURES 0 #define TCG_SVM_FEATURES 0 #define TCG_KVM_FEATURES 0 diff --git a/target/i386/translate.c b/target/i386/translate.c index 6082db2..2c64d2b 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -219,6 +219,7 @@ static const uint8_t cc_op_live[CC_OP_NB] =3D { [CC_OP_SHLB ... CC_OP_SHLQ] =3D USES_CC_DST | USES_CC_SRC, [CC_OP_SARB ... CC_OP_SARQ] =3D USES_CC_DST | USES_CC_SRC, [CC_OP_BMILGB ... CC_OP_BMILGQ] =3D USES_CC_DST | USES_CC_SRC, + [CC_OP_TBMADDB ... CC_OP_TBMADDQ] =3D USES_CC_DST | USES_CC_SRC, [CC_OP_ADCX] =3D USES_CC_DST | USES_CC_SRC, [CC_OP_ADOX] =3D USES_CC_SRC | USES_CC_SRC2, [CC_OP_ADCOX] =3D USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, @@ -783,6 +784,12 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s,= TCGv reg) t0 =3D gen_ext_tl(reg, cpu_cc_src, size, false); return (CCPrepare) { .cond =3D TCG_COND_EQ, .reg =3D t0, .mask =3D= -1 }; =20 + case CC_OP_TBMADDB ... CC_OP_TBMADDQ: + size =3D s->cc_op - CC_OP_TBMADDB; + t0 =3D gen_ext_tl(reg, cpu_cc_src, size, true); + return (CCPrepare) { .cond =3D TCG_COND_EQ, .reg =3D t0, + .mask =3D -1, .imm =3D -1 }; + case CC_OP_ADCX: case CC_OP_ADCOX: return (CCPrepare) { .cond =3D TCG_COND_NE, .reg =3D cpu_cc_dst, @@ -8291,9 +8298,119 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, gen_sse(env, s, b, pc_start, rex_r); break; =20 - case 0x800 ... 0x8ff: /* XOP opcode map 8 */ - case 0x900 ... 0x9ff: /* XOP opcode map 9 */ - case 0xa00 ... 0xaff: /* XOP opcode map 10 */ + case 0x901: + case 0x902: /* most tbm insns */ + if (!(s->cpuid_ext3_features & CPUID_EXT3_TBM) + || s->vex_l !=3D 0) { + goto illegal_op; + } + modrm =3D cpu_ldub_code(env, s->pc++); + mod =3D (modrm >> 6) & 3; + rm =3D (modrm & 7) | REX_B(s); + ot =3D rex_w > 0 ? MO_64 : MO_32; + if (mod !=3D 3) { + gen_lea_modrm(env, s, modrm); + gen_op_ld_v(s, ot, cpu_T0, cpu_A0); + } else { + gen_op_mov_v_reg(ot, cpu_T0, rm); + } + + tcg_gen_mov_tl(cpu_cc_src, cpu_T0); + switch ((b & 2) * 4 + ((modrm >> 3) & 7)) { + case 1: /* blcfill */ + op =3D CC_OP_TBMADDB; + tcg_gen_addi_tl(cpu_T1, cpu_T0, 1); + tcg_gen_and_tl(cpu_T0, cpu_T0, cpu_T1); + break; + case 2: /* blsfill */ + op =3D CC_OP_BMILGB; + tcg_gen_subi_tl(cpu_T1, cpu_T0, 1); + tcg_gen_or_tl(cpu_T0, cpu_T0, cpu_T1); + break; + case 3: /* blcs */ + op =3D CC_OP_TBMADDB; + tcg_gen_addi_tl(cpu_T1, cpu_T0, 1); + tcg_gen_or_tl(cpu_T0, cpu_T0, cpu_T1); + break; + case 4: /* tzmsk */ + op =3D CC_OP_BMILGB; + tcg_gen_subi_tl(cpu_T1, cpu_T0, 1); + tcg_gen_andc_tl(cpu_T0, cpu_T1, cpu_T0); + break; + case 5: /* blcic */ + op =3D CC_OP_TBMADDB; + tcg_gen_addi_tl(cpu_T1, cpu_T0, 1); + tcg_gen_andc_tl(cpu_T0, cpu_T1, cpu_T0); + break; + case 6: /* blsic */ + op =3D CC_OP_BMILGB; + tcg_gen_subi_tl(cpu_T1, cpu_T0, 1); + tcg_gen_orc_tl(cpu_T0, cpu_T1, cpu_T0); + break; + case 7: /* t1mskc */ + op =3D CC_OP_TBMADDB; + tcg_gen_addi_tl(cpu_T1, cpu_T0, 1); + tcg_gen_orc_tl(cpu_T0, cpu_T1, cpu_T0); + break; + case 8 + 1: /* blcmsk */ + op =3D CC_OP_TBMADDB; + tcg_gen_addi_tl(cpu_T1, cpu_T0, 1); + tcg_gen_xor_tl(cpu_T0, cpu_T0, cpu_T1); + break; + case 8 + 6: /* blci */ + op =3D CC_OP_TBMADDB; + tcg_gen_addi_tl(cpu_T1, cpu_T0, 1); + tcg_gen_orc_tl(cpu_T0, cpu_T0, cpu_T1); + break; + default: + goto illegal_op; + } + gen_op_mov_reg_v(ot, s->vex_v, cpu_T0); + tcg_gen_mov_tl(cpu_cc_src, cpu_T0); + set_cc_op(s, op + ot); + break; + + case 0xa10: /* bextr Gy, Ey, imm4 */ + { + int ofs, len, max; + + if (!(s->cpuid_ext3_features & CPUID_EXT3_TBM) + || s->vex_l !=3D 0) { + goto illegal_op; + } + + s->rip_offset =3D 4; + modrm =3D cpu_ldub_code(env, s->pc++); + reg =3D ((modrm >> 3) & 7) | rex_r; + mod =3D (modrm >> 6) & 3; + rm =3D (modrm & 7) | REX_B(s); + ot =3D rex_w > 0 ? MO_64 : MO_32; + if (mod !=3D 3) { + gen_lea_modrm(env, s, modrm); + gen_op_ld_v(s, ot, cpu_T0, cpu_A0); + } else { + gen_op_mov_v_reg(ot, cpu_T0, rm); + } + val =3D cpu_ldl_code(env, s->pc); + s->pc +=3D 4; + + ofs =3D extract32(val, 0, 8); + len =3D extract32(val, 8, 8); + max =3D 8 << ot; + if (len =3D=3D 0 || ofs >=3D max) { + tcg_gen_movi_tl(cpu_T0, 0); + } else { + len =3D MIN(len, max - ofs); + tcg_gen_extract_tl(cpu_T0, cpu_T0, ofs, len); + } + tcg_gen_mov_tl(cpu_regs[reg], cpu_T0); + gen_op_update1_cc(); + /* Z is set as per result, C/O =3D 0, S/A/P =3D undefined. + Which is less strict than LOGIC, but accurate. */ + set_cc_op(s, CC_OP_LOGICB + ot); + } + break; + default: goto unknown_op; } --=20 2.9.4