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[173.197.98.123]) by smtp.gmail.com with ESMTPSA id o8sm21619584pgn.52.2017.07.10.00.35.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Jul 2017 00:36:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uJ0ERl9gFUaXigxow/y7TjEG1XkDxYWJS3OrFqLW6VI=; b=D/rrLGsvMlGUqOG5CBnRVarr9IpSVz7ehVKJ3aqQ95PraffteLIuvy9VGk7VxznSeX 3ZXMufr/bf6iGzymhMRYv+zG7ho9G7otUjZn+owF7/t8b2OUo4a8rf1O6aqMVhBg7SvM IpWha/y+cFParAS70k5ixYsWO5EgfdYX6CPedUUEmUkr7aY2j3larsXG3p2vRzowQVtf dw3isZF9gGcUkmD5AicDTNFSMseByJPkKyF52amKbIVyWXsCphQZBzUAc/dz0d3nikhc 9+oiULPNjFt4E8woVdrR+griv4D0njTk8EG7rx+xXZGuojb4/uNby/pWM3XHP+ti4mOq RWuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=uJ0ERl9gFUaXigxow/y7TjEG1XkDxYWJS3OrFqLW6VI=; b=HvBvUAe+ak2koB7d2xHHt4I7tU/7LbZ3QrBrz6gIgC9ve2sO8BtbqZy6zoR9OvB2Sy ko9xY15zGgbZRm1U0FOQGzr9V7dMf9NoHlhR7HwcO7D6G+YlO0ZkeAz7VGINN7H9GkDl WiN6rvl93AHz7EkVgzGc/cO3PaiBpXAIeEV00CMild0rwhwcomcfj1gc34yVWdPpzCDD uJTZFo2WOPtDYA/LGkm3mVD98Ec+427g2Se3dBAixAqZeowSBh5SnjR0gzJ4bP5poikz 5pq13kf/ZHp56wyYgSSqAFHT66GX7vizKB3ey6udswyEsg+YyHw09Vx/8coXUPz1UAFm 1Bhw== X-Gm-Message-State: AIVw113RgM0t759gfbPEKm+tN/GqYGJM8HryR0ZJBjwRdvjigv7irmLK bmMKl4SOJCk6BlDS9JI= X-Received: by 10.84.191.165 with SMTP id a34mr16382381pld.243.1499672171490; Mon, 10 Jul 2017 00:36:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 9 Jul 2017 21:34:59 -1000 Message-Id: <20170710073501.5207-4-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170710073501.5207-1-rth@twiddle.net> References: <20170710073501.5207-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 74.125.83.52 Subject: [Qemu-devel] [PULL 3/5] tcg/aarch64: Enable indirect jump path using LDR (literal) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Pranith Kumar , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Pranith Kumar This patch enables the indirect jump path using an LDR (literal) instruction. It will be interesting to test and see which performs better among the two paths. CC: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Pranith Kumar Message-Id: <20170630143614.31059-3-bobby.prani@gmail.com> Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 42 ++++++++++++++++++++++++++++------------= -- 1 file changed, 28 insertions(+), 14 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index a84422d..04bc369 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -269,6 +269,8 @@ typedef enum { I3207_BLR =3D 0xd63f0000, I3207_RET =3D 0xd65f0000, =20 + /* Load literal for loading the address at pc-relative offset */ + I3305_LDR =3D 0x58000000, /* Load/store register. Described here as 3.3.12, but the helper that emits them can transform to 3.3.10 or 3.3.13. */ I3312_STRB =3D 0x38000000 | LDST_ST << 22 | MO_8 << 30, @@ -389,6 +391,11 @@ static inline uint32_t tcg_in32(TCGContext *s) #define tcg_out_insn(S, FMT, OP, ...) \ glue(tcg_out_insn_,FMT)(S, glue(glue(glue(I,FMT),_),OP), ## __VA_ARGS_= _) =20 +static void tcg_out_insn_3305(TCGContext *s, AArch64Insn insn, int imm19, = TCGReg rt) +{ + tcg_out32(s, insn | (imm19 & 0x7ffff) << 5 | rt); +} + static void tcg_out_insn_3201(TCGContext *s, AArch64Insn insn, TCGType ext, TCGReg rt, int imm19) { @@ -864,6 +871,8 @@ static inline void tcg_out_call(TCGContext *s, tcg_insn= _unit *target) } } =20 +#ifdef USE_DIRECT_JUMP + void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr) { tcg_insn_unit i1, i2; @@ -889,6 +898,8 @@ void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uint= ptr_t addr) flush_icache_range(jmp_addr, jmp_addr + 8); } =20 +#endif + static inline void tcg_out_goto_label(TCGContext *s, TCGLabel *l) { if (!l->has_value) { @@ -1400,21 +1411,24 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_goto_tb: -#ifndef USE_DIRECT_JUMP -#error "USE_DIRECT_JUMP required for aarch64" -#endif - /* consistency for USE_DIRECT_JUMP */ - tcg_debug_assert(s->tb_jmp_insn_offset !=3D NULL); - /* Ensure that ADRP+ADD are 8-byte aligned so that an atomic - write can be used to patch the target address. */ - if ((uintptr_t)s->code_ptr & 7) { - tcg_out32(s, NOP); + if (s->tb_jmp_insn_offset !=3D NULL) { + /* USE_DIRECT_JUMP */ + /* Ensure that ADRP+ADD are 8-byte aligned so that an atomic + write can be used to patch the target address. */ + if ((uintptr_t)s->code_ptr & 7) { + tcg_out32(s, NOP); + } + s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); + /* actual branch destination will be patched by + aarch64_tb_set_jmp_target later. */ + tcg_out_insn(s, 3406, ADRP, TCG_REG_TMP, 0); + tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_TMP, TCG_REG= _TMP, 0); + } else { + /* !USE_DIRECT_JUMP */ + tcg_debug_assert(s->tb_jmp_target_addr !=3D NULL); + intptr_t offset =3D tcg_pcrel_diff(s, (s->tb_jmp_target_addr += a0)) >> 2; + tcg_out_insn(s, 3305, LDR, offset, TCG_REG_TMP); } - s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); - /* actual branch destination will be patched by - aarch64_tb_set_jmp_target later. */ - tcg_out_insn(s, 3406, ADRP, TCG_REG_TMP, 0); - tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_TMP, TCG_REG_TMP= , 0); tcg_out_insn(s, 3207, BR, TCG_REG_TMP); s->tb_jmp_reset_offset[a0] =3D tcg_current_code_size(s); break; --=20 2.9.4