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[66.91.136.156]) by smtp.gmail.com with ESMTPSA id i85sm1407176qke.66.2017.07.06.19.24.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jul 2017 19:24:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=7sficcX29WEwhyfUIUIlPqDMP1Gs2uHB4tuikurdzPo=; b=ESj+vcBqZJR2j3D6Hr5pAUGv2rIs2e27AXBukBc4naLMWyI4wSQbNjUaorQ69wBk97 qeyHZo2D+SM48cHZ7gLQ9td8lN/OHIClfiZf0BtGaWbIFkmhoeMH/kPHa0fTAcT9bSPx wKup5P9H8JRZLUG0xNeWwylJNR/ypGSn8kljZQUmlx3Q0J4KrL1yzIoqHfXLNTV4bUrW tx4JC/jWoyWFZzK3m0B5sUIi7oUwzVkIOezMqHVY93MftucyuPfp5QffT5603yLT/oLa BdDlGvLsL3kVpbFbO/bDQ3TdjXQODSWHbvpXtmmK/ea8DUHPB+rL42FsnqPzb39fY16D lg0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=7sficcX29WEwhyfUIUIlPqDMP1Gs2uHB4tuikurdzPo=; b=WN7/S26xfib1b/oW23k2y4YiaEpmtucQW3K6rK8nUMOA1JvL87cyNed1hvUmjoEEc7 iHg9DV89fqycyhH0FTF15sIGuMM3QKTx0GBYieApvlOKS4tooiK+w1BnvDBDb0V+bYh+ AjOO5uQWtl5P2R899jp2hLmuIvGrAeA58YU0i7o6LlU9QiedTYxWxOfE76+v54fca+2j YOMgCHnuBWwZUCqKEHkEIYvaOJtiwSY8N7Sc+cF+DvhcZ5X/5JokBb/5bU2Uasod/R55 BN7b7/nHBA72foy1lMcctgPeIlU+9G3iu5963KGWxaozAw+Si12cbIGKpOR40yEji61k 4sLg== X-Gm-Message-State: AKS2vOzBjPeicrvi5UX3TZwFRUiRCmZauTqnK+6v/5w0YoYEXd7zy//2 0KNacr7orYO+cHX4X2Q= X-Received: by 10.55.79.131 with SMTP id d125mr61605777qkb.169.1499394272279; Thu, 06 Jul 2017 19:24:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 6 Jul 2017 16:21:00 -1000 Message-Id: <20170707022111.21836-17-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170707022111.21836-1-rth@twiddle.net> References: <20170707022111.21836-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH v2 16/27] target/sh4: Load/store Dr as 64-bit quantities X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno@clisp.org, laurent@vivier.eu, aurelien@aurel32.net, glaubitz@debian.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This enforces proper alignment and makes the register update more natural. Note that there is a more serious bug fix for fmov {DX}Rn,@(R0,Rn) to use a store instead of a load. Signed-off-by: Richard Henderson --- target/sh4/translate.c | 74 ++++++++++++++++++++++++----------------------= ---- 1 file changed, 35 insertions(+), 39 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 616e615..fcdabe8 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1004,12 +1004,10 @@ static void _decode_opc(DisasContext * ctx) case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { - TCGv addr_hi =3D tcg_temp_new(); - int fr =3D XHACK(B7_4); - tcg_gen_addi_i32(addr_hi, REG(B11_8), 4); - tcg_gen_qemu_st_i32(FREG(fr), REG(B11_8), ctx->memidx, MO_TEUL= ); - tcg_gen_qemu_st_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEU= L); - tcg_temp_free(addr_hi); + TCGv_i64 fp =3D tcg_temp_new_i64(); + gen_load_fpr64(ctx, fp, XHACK(B7_4)); + tcg_gen_qemu_st_i64(fp, REG(B11_8), ctx->memidx, MO_TEQ); + tcg_temp_free_i64(fp); } else { tcg_gen_qemu_st_i32(FREG(B7_4), REG(B11_8), ctx->memidx, MO_TE= UL); } @@ -1017,12 +1015,10 @@ static void _decode_opc(DisasContext * ctx) case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { - TCGv addr_hi =3D tcg_temp_new(); - int fr =3D XHACK(B11_8); - tcg_gen_addi_i32(addr_hi, REG(B7_4), 4); - tcg_gen_qemu_ld_i32(FREG(fr), REG(B7_4), ctx->memidx, MO_TEUL); - tcg_gen_qemu_ld_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEU= L); - tcg_temp_free(addr_hi); + TCGv_i64 fp =3D tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(fp, REG(B7_4), ctx->memidx, MO_TEQ); + gen_store_fpr64(ctx, fp, XHACK(B11_8)); + tcg_temp_free_i64(fp); } else { tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TE= UL); } @@ -1030,13 +1026,11 @@ static void _decode_opc(DisasContext * ctx) case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { - TCGv addr_hi =3D tcg_temp_new(); - int fr =3D XHACK(B11_8); - tcg_gen_addi_i32(addr_hi, REG(B7_4), 4); - tcg_gen_qemu_ld_i32(FREG(fr), REG(B7_4), ctx->memidx, MO_TEUL); - tcg_gen_qemu_ld_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEU= L); - tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8); - tcg_temp_free(addr_hi); + TCGv_i64 fp =3D tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(fp, REG(B7_4), ctx->memidx, MO_TEQ); + gen_store_fpr64(ctx, fp, XHACK(B11_8)); + tcg_temp_free_i64(fp); + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8); } else { tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TE= UL); tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); @@ -1044,18 +1038,20 @@ static void _decode_opc(DisasContext * ctx) return; case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED - TCGv addr =3D tcg_temp_new_i32(); - tcg_gen_subi_i32(addr, REG(B11_8), 4); - if (ctx->tbflags & FPSCR_SZ) { - int fr =3D XHACK(B7_4); - tcg_gen_qemu_st_i32(FREG(fr + 1), addr, ctx->memidx, MO_TEUL); - tcg_gen_subi_i32(addr, addr, 4); - tcg_gen_qemu_st_i32(FREG(fr), addr, ctx->memidx, MO_TEUL); - } else { - tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL); - } - tcg_gen_mov_i32(REG(B11_8), addr); - tcg_temp_free(addr); + { + TCGv addr =3D tcg_temp_new_i32(); + if (ctx->tbflags & FPSCR_SZ) { + TCGv_i64 fp =3D tcg_temp_new_i64(); + gen_load_fpr64(ctx, fp, XHACK(B7_4)); + tcg_gen_qemu_st_i64(fp, addr, ctx->memidx, MO_TEQ); + tcg_temp_free_i64(fp); + } else { + tcg_gen_subi_i32(addr, REG(B11_8), 4); + tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL= ); + } + tcg_gen_mov_i32(REG(B11_8), addr); + tcg_temp_free(addr); + } return; case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ CHECK_FPU_ENABLED @@ -1063,10 +1059,10 @@ static void _decode_opc(DisasContext * ctx) TCGv addr =3D tcg_temp_new_i32(); tcg_gen_add_i32(addr, REG(B7_4), REG(0)); if (ctx->tbflags & FPSCR_SZ) { - int fr =3D XHACK(B11_8); - tcg_gen_qemu_ld_i32(FREG(fr), addr, ctx->memidx, MO_TEUL); - tcg_gen_addi_i32(addr, addr, 4); - tcg_gen_qemu_ld_i32(FREG(fr + 1), addr, ctx->memidx, MO_TE= UL); + TCGv_i64 fp =3D tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(fp, addr, ctx->memidx, MO_TEQ); + gen_store_fpr64(ctx, fp, XHACK(B11_8)); + tcg_temp_free_i64(fp); } else { tcg_gen_qemu_ld_i32(FREG(B11_8), addr, ctx->memidx, MO_TEU= L); } @@ -1079,10 +1075,10 @@ static void _decode_opc(DisasContext * ctx) TCGv addr =3D tcg_temp_new(); tcg_gen_add_i32(addr, REG(B11_8), REG(0)); if (ctx->tbflags & FPSCR_SZ) { - int fr =3D XHACK(B7_4); - tcg_gen_qemu_ld_i32(FREG(fr), addr, ctx->memidx, MO_TEUL); - tcg_gen_addi_i32(addr, addr, 4); - tcg_gen_qemu_ld_i32(FREG(fr + 1), addr, ctx->memidx, MO_TE= UL); + TCGv_i64 fp =3D tcg_temp_new_i64(); + gen_load_fpr64(ctx, fp, XHACK(B7_4)); + tcg_gen_qemu_st_i64(fp, addr, ctx->memidx, MO_TEQ); + tcg_temp_free_i64(fp); } else { tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL= ); } --=20 2.9.4