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[66.91.136.156]) by smtp.gmail.com with ESMTPSA id i85sm1407176qke.66.2017.07.06.19.23.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jul 2017 19:24:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=SDZwY1f0ZHmUjqRlCSkL4vIMwaaWxaH0BPBE2rwQLFY=; b=pol3oRnhAVIjLOsmGjyX/w5Kfeod3Fku8fByjBLhrGO9Jny8+2kOUUM8CN6KDYlbCS 7z+cVnSxNvcGKijdWhFxjtaO1WFp4SgvTOI/mbdQnltZR0PH4DXQoP7CiftMdh2z6Hgp bLMOuEVpYlpeJQSs6jmTq8YBsSsoT/OZdZs6K3aceUELHtT+mwWuKyXWOpsDM0iLeVQ2 h3DLzxT89RDx7yH/Cs5Vxcf2ENIN2hKmMJQaIL2F11a7lQzBsTaU16m5UYR3j5cvaia4 Qev/DxxJQLf0zHUq0dcOjp6Jc+PAkzY5Ldxnu1FrdwjPBhiAQPQq2epPqZtwqGJoPeYG tNGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=SDZwY1f0ZHmUjqRlCSkL4vIMwaaWxaH0BPBE2rwQLFY=; b=bgtby8YKlwLR3vgRe/3ZwQdxpQgrvl7bc3JoVsSAQOVcBxCHEB8Og0v3kXZVBJwEMA IyU9qRbyAuvkj89C2MXmOFQrLrwsPygvoflLCqJt7jPclna1rsnynMrOqGnpPlL5Z0HQ f489qwY+c5zsUr9pPjaNg0rYnfzasVANi5qFphLTfzScIyKHmz6cR3DmwczQ5/7mR7Ul KtZEL/mLaZ6KZfAVfn0lL6TJdlxIQBO+79Z88bqJrJFiWedOHM4R+/gDCY4k7jjlHTlH 3Ru0JHJlXmFrwCeJWzby9VP9SL/wOi9kyHIHBZ4JxuzRHpKm0EW80u9DuieQqqfpyAar UJRg== X-Gm-Message-State: AKS2vOydeQi3SIoECIF0HcMql11f5aELm5rdAmWL6OXTNnrnhYOn83it AJ0wwoWmE3WksDS86mA= X-Received: by 10.237.61.91 with SMTP id h27mr70172819qtf.1.1499394250762; Thu, 06 Jul 2017 19:24:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 6 Jul 2017 16:20:55 -1000 Message-Id: <20170707022111.21836-12-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170707022111.21836-1-rth@twiddle.net> References: <20170707022111.21836-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::244 Subject: [Qemu-devel] [PATCH v2 11/27] target/sh4: Unify cpu_fregs into FREG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno@clisp.org, laurent@vivier.eu, aurelien@aurel32.net, glaubitz@debian.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We were treating FREG as an index and REG as a TCGv. Making FREG return a TCGv is both less confusing and a step toward cleaner banking of cpu_fregs. Signed-off-by: Richard Henderson Reviewed-by: Aurelien Jarno Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/sh4/translate.c | 125 ++++++++++++++++++++-------------------------= ---- 1 file changed, 52 insertions(+), 73 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 0ac101e..b521cff 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -366,10 +366,11 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int r= eg) #define REG(x) cpu_gregs[(x) ^ ctx->gbank] #define ALTREG(x) cpu_gregs[(x) ^ ctx->gbank ^ 0x10] =20 -#define FREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)) +#define FREG(x) cpu_fregs[ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)] #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) -#define XREG(x) (ctx->tbflags & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x)) -#define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */ +#define XREG(x) FREG(XHACK(x)) +/* Assumes lsb of (x) is always 0 */ +#define DREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)) =20 #define CHECK_NOT_DELAY_SLOT \ if (ctx->envflags & DELAY_SLOT_MASK) { \ @@ -989,56 +990,51 @@ static void _decode_opc(DisasContext * ctx) CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { TCGv_i64 fp =3D tcg_temp_new_i64(); - gen_load_fpr64(fp, XREG(B7_4)); - gen_store_fpr64(fp, XREG(B11_8)); + gen_load_fpr64(fp, XHACK(B7_4)); + gen_store_fpr64(fp, XHACK(B11_8)); tcg_temp_free_i64(fp); } else { - tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); + tcg_gen_mov_i32(FREG(B11_8), FREG(B7_4)); } return; case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { TCGv addr_hi =3D tcg_temp_new(); - int fr =3D XREG(B7_4); + int fr =3D XHACK(B7_4); tcg_gen_addi_i32(addr_hi, REG(B11_8), 4); - tcg_gen_qemu_st_i32(cpu_fregs[fr], REG(B11_8), - ctx->memidx, MO_TEUL); - tcg_gen_qemu_st_i32(cpu_fregs[fr+1], addr_hi, - ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(FREG(fr), REG(B11_8), ctx->memidx, MO_TEUL= ); + tcg_gen_qemu_st_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEU= L); tcg_temp_free(addr_hi); } else { - tcg_gen_qemu_st_i32(cpu_fregs[FREG(B7_4)], REG(B11_8), - ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(FREG(B7_4), REG(B11_8), ctx->memidx, MO_TE= UL); } return; case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { TCGv addr_hi =3D tcg_temp_new(); - int fr =3D XREG(B11_8); + int fr =3D XHACK(B11_8); tcg_gen_addi_i32(addr_hi, REG(B7_4), 4); - tcg_gen_qemu_ld_i32(cpu_fregs[fr], REG(B7_4), ctx->memidx, MO_= TEUL); - tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr_hi, ctx->memidx, MO_= TEUL); + tcg_gen_qemu_ld_i32(FREG(fr), REG(B7_4), ctx->memidx, MO_TEUL); + tcg_gen_qemu_ld_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEU= L); tcg_temp_free(addr_hi); } else { - tcg_gen_qemu_ld_i32(cpu_fregs[FREG(B11_8)], REG(B7_4), - ctx->memidx, MO_TEUL); + tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TE= UL); } return; case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { TCGv addr_hi =3D tcg_temp_new(); - int fr =3D XREG(B11_8); + int fr =3D XHACK(B11_8); tcg_gen_addi_i32(addr_hi, REG(B7_4), 4); - tcg_gen_qemu_ld_i32(cpu_fregs[fr], REG(B7_4), ctx->memidx, MO_= TEUL); - tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr_hi, ctx->memidx, MO_= TEUL); + tcg_gen_qemu_ld_i32(FREG(fr), REG(B7_4), ctx->memidx, MO_TEUL); + tcg_gen_qemu_ld_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEU= L); tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8); tcg_temp_free(addr_hi); } else { - tcg_gen_qemu_ld_i32(cpu_fregs[FREG(B11_8)], REG(B7_4), - ctx->memidx, MO_TEUL); + tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TE= UL); tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); } return; @@ -1047,13 +1043,12 @@ static void _decode_opc(DisasContext * ctx) TCGv addr =3D tcg_temp_new_i32(); tcg_gen_subi_i32(addr, REG(B11_8), 4); if (ctx->tbflags & FPSCR_SZ) { - int fr =3D XREG(B7_4); - tcg_gen_qemu_st_i32(cpu_fregs[fr+1], addr, ctx->memidx, MO_TEU= L); + int fr =3D XHACK(B7_4); + tcg_gen_qemu_st_i32(FREG(fr + 1), addr, ctx->memidx, MO_TEUL); tcg_gen_subi_i32(addr, addr, 4); - tcg_gen_qemu_st_i32(cpu_fregs[fr], addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(FREG(fr), addr, ctx->memidx, MO_TEUL); } else { - tcg_gen_qemu_st_i32(cpu_fregs[FREG(B7_4)], addr, - ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL); } tcg_gen_mov_i32(REG(B11_8), addr); tcg_temp_free(addr); @@ -1064,15 +1059,12 @@ static void _decode_opc(DisasContext * ctx) TCGv addr =3D tcg_temp_new_i32(); tcg_gen_add_i32(addr, REG(B7_4), REG(0)); if (ctx->tbflags & FPSCR_SZ) { - int fr =3D XREG(B11_8); - tcg_gen_qemu_ld_i32(cpu_fregs[fr], addr, - ctx->memidx, MO_TEUL); + int fr =3D XHACK(B11_8); + tcg_gen_qemu_ld_i32(FREG(fr), addr, ctx->memidx, MO_TEUL); tcg_gen_addi_i32(addr, addr, 4); - tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr, - ctx->memidx, MO_TEUL); + tcg_gen_qemu_ld_i32(FREG(fr + 1), addr, ctx->memidx, MO_TE= UL); } else { - tcg_gen_qemu_ld_i32(cpu_fregs[FREG(B11_8)], addr, - ctx->memidx, MO_TEUL); + tcg_gen_qemu_ld_i32(FREG(B11_8), addr, ctx->memidx, MO_TEU= L); } tcg_temp_free(addr); } @@ -1083,15 +1075,12 @@ static void _decode_opc(DisasContext * ctx) TCGv addr =3D tcg_temp_new(); tcg_gen_add_i32(addr, REG(B11_8), REG(0)); if (ctx->tbflags & FPSCR_SZ) { - int fr =3D XREG(B7_4); - tcg_gen_qemu_ld_i32(cpu_fregs[fr], addr, - ctx->memidx, MO_TEUL); + int fr =3D XHACK(B7_4); + tcg_gen_qemu_ld_i32(FREG(fr), addr, ctx->memidx, MO_TEUL); tcg_gen_addi_i32(addr, addr, 4); - tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr, - ctx->memidx, MO_TEUL); + tcg_gen_qemu_ld_i32(FREG(fr + 1), addr, ctx->memidx, MO_TE= UL); } else { - tcg_gen_qemu_st_i32(cpu_fregs[FREG(B7_4)], addr, - ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL= ); } tcg_temp_free(addr); } @@ -1139,34 +1128,28 @@ static void _decode_opc(DisasContext * ctx) } else { switch (ctx->opcode & 0xf00f) { case 0xf000: /* fadd Rm,Rn */ - gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_env, - cpu_fregs[FREG(B11_8)], - cpu_fregs[FREG(B7_4)]); + gen_helper_fadd_FT(FREG(B11_8), cpu_env, + FREG(B11_8), FREG(B7_4)); break; case 0xf001: /* fsub Rm,Rn */ - gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_env, - cpu_fregs[FREG(B11_8)], - cpu_fregs[FREG(B7_4)]); + gen_helper_fsub_FT(FREG(B11_8), cpu_env, + FREG(B11_8), FREG(B7_4)); break; case 0xf002: /* fmul Rm,Rn */ - gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_env, - cpu_fregs[FREG(B11_8)], - cpu_fregs[FREG(B7_4)]); + gen_helper_fmul_FT(FREG(B11_8), cpu_env, + FREG(B11_8), FREG(B7_4)); break; case 0xf003: /* fdiv Rm,Rn */ - gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_env, - cpu_fregs[FREG(B11_8)], - cpu_fregs[FREG(B7_4)]); + gen_helper_fdiv_FT(FREG(B11_8), cpu_env, + FREG(B11_8), FREG(B7_4)); break; case 0xf004: /* fcmp/eq Rm,Rn */ gen_helper_fcmp_eq_FT(cpu_sr_t, cpu_env, - cpu_fregs[FREG(B11_8)], - cpu_fregs[FREG(B7_4)]); + FREG(B11_8), FREG(B7_4)); return; case 0xf005: /* fcmp/gt Rm,Rn */ gen_helper_fcmp_gt_FT(cpu_sr_t, cpu_env, - cpu_fregs[FREG(B11_8)], - cpu_fregs[FREG(B7_4)]); + FREG(B11_8), FREG(B7_4)); return; } } @@ -1178,9 +1161,8 @@ static void _decode_opc(DisasContext * ctx) if (ctx->tbflags & FPSCR_PR) { break; /* illegal instruction */ } else { - gen_helper_fmac_FT(cpu_fregs[FREG(B11_8)], cpu_env, - cpu_fregs[FREG(0)], cpu_fregs[FREG(B7_4= )], - cpu_fregs[FREG(B11_8)]); + gen_helper_fmac_FT(FREG(B11_8), cpu_env, + FREG(0), FREG(B7_4), FREG(B11_8)); return; } } @@ -1718,11 +1700,11 @@ static void _decode_opc(DisasContext * ctx) return; case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ CHECK_FPU_ENABLED - tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fpul); + tcg_gen_mov_i32(FREG(B11_8), cpu_fpul); return; case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */ CHECK_FPU_ENABLED - tcg_gen_mov_i32(cpu_fpul, cpu_fregs[FREG(B11_8)]); + tcg_gen_mov_i32(cpu_fpul, FREG(B11_8)); return; case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Fla= g] */ CHECK_FPU_ENABLED @@ -1736,7 +1718,7 @@ static void _decode_opc(DisasContext * ctx) tcg_temp_free_i64(fp); } else { - gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_env, cpu_fpul); + gen_helper_float_FT(FREG(B11_8), cpu_env, cpu_fpul); } return; case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag= ] */ @@ -1751,18 +1733,16 @@ static void _decode_opc(DisasContext * ctx) tcg_temp_free_i64(fp); } else { - gen_helper_ftrc_FT(cpu_fpul, cpu_env, cpu_fregs[FREG(B11_8)]); + gen_helper_ftrc_FT(cpu_fpul, cpu_env, FREG(B11_8)); } return; case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ CHECK_FPU_ENABLED - tcg_gen_xori_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], - 0x80000000); + tcg_gen_xori_i32(FREG(B11_8), FREG(B11_8), 0x80000000); return; case 0xf05d: /* fabs FRn/DRn - FPCSR: Nothing */ CHECK_FPU_ENABLED - tcg_gen_andi_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], - 0x7fffffff); + tcg_gen_andi_i32(FREG(B11_8), FREG(B11_8), 0x7fffffff); return; case 0xf06d: /* fsqrt FRn */ CHECK_FPU_ENABLED @@ -1775,8 +1755,7 @@ static void _decode_opc(DisasContext * ctx) gen_store_fpr64(fp, DREG(B11_8)); tcg_temp_free_i64(fp); } else { - gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_env, - cpu_fregs[FREG(B11_8)]); + gen_helper_fsqrt_FT(FREG(B11_8), cpu_env, FREG(B11_8)); } return; case 0xf07d: /* fsrra FRn */ @@ -1785,13 +1764,13 @@ static void _decode_opc(DisasContext * ctx) case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ CHECK_FPU_ENABLED if (!(ctx->tbflags & FPSCR_PR)) { - tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0); + tcg_gen_movi_i32(FREG(B11_8), 0); } return; case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ CHECK_FPU_ENABLED if (!(ctx->tbflags & FPSCR_PR)) { - tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000); + tcg_gen_movi_i32(FREG(B11_8), 0x3f800000); } return; case 0xf0ad: /* fcnvsd FPUL,DRn */ --=20 2.9.4