From nobody Sat Feb 7 09:34:57 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499394431895490.40344410171383; Thu, 6 Jul 2017 19:27:11 -0700 (PDT) Received: from localhost ([::1]:54123 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dTIz8-00058L-Fq for importer@patchew.org; Thu, 06 Jul 2017 22:27:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34490) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dTIvI-0001uB-7M for qemu-devel@nongnu.org; Thu, 06 Jul 2017 22:23:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dTIvH-0000DV-4M for qemu-devel@nongnu.org; Thu, 06 Jul 2017 22:23:12 -0400 Received: from mail-qt0-x243.google.com ([2607:f8b0:400d:c0d::243]:35261) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dTIvH-0000DG-04 for qemu-devel@nongnu.org; Thu, 06 Jul 2017 22:23:11 -0400 Received: by mail-qt0-x243.google.com with SMTP id w12so2709738qta.2 for ; Thu, 06 Jul 2017 19:23:10 -0700 (PDT) Received: from bigtime.twiddle.net.com (rrcs-66-91-136-156.west.biz.rr.com. [66.91.136.156]) by smtp.gmail.com with ESMTPSA id i85sm1407176qke.66.2017.07.06.19.23.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jul 2017 19:23:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=WTaoeEfavtPvI5eagfJlm5QmLGTgfZdYJ/gmiB5MhnY=; b=kuXJegeu5a8bE09obQN5UbjXVc72UveJ6QLTgeNOvVpV8hl+rGi90DbsD4YhZbSfFO yv4OyFMaQi5SMoy8tgGyENE24c1qH2osPvqFk8zLl0/XbZ3G6tlQqHbrn7Qqf9VEPik7 Ng0UxfNJIkAI/ds2U0ym6Ff1XNgXzL7NHreZIm5Uz1WitukNLUg8Utg8Js3UuWOUpnNb RDw0EtUKiIpEToID0yRRqOCgiRr/fd0/mYMVnT2auEd3TNmJw/f/QRRrhv5HNjddhV+/ mGfRqI7btscPAPDuOwPEnBaMSV/S47sZBYToIefDRIhpfjkTg1agwAlnqllgQCBrRwYe BeVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=WTaoeEfavtPvI5eagfJlm5QmLGTgfZdYJ/gmiB5MhnY=; b=QH2kZqjkpOpWgSNIu92doVR/NB7y8ATCjDwU1bx5/UCTOE4O0vdyxbVEyb9xec+wFR PbMU5LZsDPWWeq9lIzxCQR47lCViwrKtMHshIMmySxWNZkYZRQg+PI2Yh4roVOFYhLDX R8J/W5BIW992psOnjlJ/wiaYxS2g0363eK3iADJM0sUgI3Dw41fHrApfbvkjSV9CbljZ U1b5zMgkNnW1/03F2PO8PKNzeWamgbh3KJ3Zwv4eknS2CS/IcdFV9sT/dXUysTZ+NqrQ ZcO8Jn082OS8S0MMAlJocD58gAtKGxx6DUEHHO3jZ87WPm3BIalFg1YARwG0xUPuecWK C+7Q== X-Gm-Message-State: AKS2vOxkjDLFG8nALKXlT/HZOxTnXwTHiICQX0SSPJJc61U4g9cwEy5u 1osYxZDsqPsmL8XEXyk= X-Received: by 10.200.52.129 with SMTP id w1mr64461419qtb.77.1499394190322; Thu, 06 Jul 2017 19:23:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 6 Jul 2017 16:20:54 -1000 Message-Id: <20170707022111.21836-11-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170707022111.21836-1-rth@twiddle.net> References: <20170707022111.21836-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::243 Subject: [Qemu-devel] [PATCH v2 10/27] target/sh4: Hoist register bank selection X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno@clisp.org, laurent@vivier.eu, aurelien@aurel32.net, glaubitz@debian.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Compute which register bank to use once at the start of translation. Signed-off-by: Richard Henderson Reviewed-by: Aurelien Jarno --- target/sh4/translate.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 73b3e02..0ac101e 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -41,6 +41,7 @@ typedef struct DisasContext { uint32_t envflags; /* should stay in sync with env->flags using TCG = ops */ int bstate; int memidx; + int gbank; uint32_t delayed_pc; int singlestep_enabled; uint32_t features; @@ -64,7 +65,7 @@ enum { =20 /* global register indexes */ static TCGv_env cpu_env; -static TCGv cpu_gregs[24]; +static TCGv cpu_gregs[32]; static TCGv cpu_sr, cpu_sr_m, cpu_sr_q, cpu_sr_t; static TCGv cpu_pc, cpu_ssr, cpu_spc, cpu_gbr; static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl; @@ -99,16 +100,19 @@ void sh4_translate_init(void) "FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1", }; =20 - if (done_init) + if (done_init) { return; + } =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); tcg_ctx.tcg_env =3D cpu_env; =20 - for (i =3D 0; i < 24; i++) + for (i =3D 0; i < 24; i++) { cpu_gregs[i] =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUSH4State, gregs[= i]), gregnames[i]); + } + memcpy(cpu_gregs + 24, cpu_gregs + 8, 8 * sizeof(TCGv)); =20 cpu_pc =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUSH4State, pc), "PC"); @@ -359,13 +363,8 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int re= g) #define B11_8 ((ctx->opcode >> 8) & 0xf) #define B15_12 ((ctx->opcode >> 12) & 0xf) =20 -#define REG(x) ((x) < 8 && (ctx->tbflags & (1u << SR_MD))\ - && (ctx->tbflags & (1u << SR_RB))\ - ? (cpu_gregs[x + 16]) : (cpu_gregs[x])) - -#define ALTREG(x) ((x) < 8 && (!(ctx->tbflags & (1u << SR_MD))\ - || !(ctx->tbflags & (1u << SR_RB)))\ - ? (cpu_gregs[x + 16]) : (cpu_gregs[x])) +#define REG(x) cpu_gregs[(x) ^ ctx->gbank] +#define ALTREG(x) cpu_gregs[(x) ^ ctx->gbank ^ 0x10] =20 #define FREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)) #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) @@ -2272,6 +2271,8 @@ void gen_intermediate_code(CPUSH4State * env, struct = TranslationBlock *tb) ctx.singlestep_enabled =3D cs->singlestep_enabled; ctx.features =3D env->features; ctx.has_movcal =3D (ctx.tbflags & TB_FLAG_PENDING_MOVCA); + ctx.gbank =3D ((ctx.tbflags & (1 << SR_MD)) && + (ctx.tbflags & (1 << SR_RB))) * 0x10; =20 max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { --=20 2.9.4