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[66.91.136.156]) by smtp.gmail.com with ESMTPSA id u85sm371825qku.42.2017.07.05.17.24.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Jul 2017 17:24:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=Zp8YYJ2hiucuGOTk/wf7u4b8kU479haBP6qTewRFrjM=; b=t3JlwPR4cK/xtaCe+QEwO18O2CrEEDgrV2Chw7nytZeOgxeBN88K6qMa62suHv01gw QQD2VBKUc0NUUo0qG7pr+myHFaSy0ipixVyW12jkVNavQ6kQwxIxIjlQNpvOKq4Gi2Bl xlv2qmr0/1pnYe8Rdq0fzBP1WLzMgZUm0qOwh4duglNqojrmKVg87uafIKq0mnUeW2wj P+XRbGIsMbCpnxXq63LXfX7pAGUcw7flQfKWp9trGdc1hM4gnVcnPux6FUFy4bYSbHSI AvWVSFEdxtqNDCxNK8/0ISHQR9WTRX+lCI8UGOmizbAmeaePGBo9v8rs//ExX69/oku0 gHdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=Zp8YYJ2hiucuGOTk/wf7u4b8kU479haBP6qTewRFrjM=; b=P5tiu1VsnXqQdnCDAMnaqJSDm9cMsjE5x8Ojvw10ScWuJQm6G1Snh+fakko/wggAJS 9yJQ0e8v0/w3XmiwP0BlpmdI8rJvCNRLtVK7ahcPWKkGCqgcty33e8vLrJ2RVe73X4Lv tyMbxgVoK2zwhVIqDmWeYDxDGWV4D0LgAjLiHaigbXoHGXK8eASQr5DqDGcLfo3TZa6f TDs5oyhDoveFJ2nzkgudngY5D+QmciraOcJV+14YWJx0DhWW+xDt3wQXAlBjizBE7uEA F9mmbzWpYwqWn+szT7qPKAZ+810jQgW/uGMpzEpK4PAZo/iePSCRKtT07NKNL4oAtcoN gnug== X-Gm-Message-State: AKS2vOz6Ap8GmeXVot74+rAtQuRr//j1Un5AHx+qz/z09lmxHP8wN/el kpIMrmPcabm195DvjZE= X-Received: by 10.55.181.71 with SMTP id e68mr54912742qkf.91.1499300680312; Wed, 05 Jul 2017 17:24:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 5 Jul 2017 14:23:56 -1000 Message-Id: <20170706002401.10507-7-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170706002401.10507-1-rth@twiddle.net> References: <20170706002401.10507-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-devel] [PATCH 06/11] target/sh4: Hoist register bank selection X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno@clisp.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Compute which register bank to use once at the start of translation. Signed-off-by: Richard Henderson --- target/sh4/translate.c | 43 ++++++++++++++++++++++++++++++------------- 1 file changed, 30 insertions(+), 13 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 9ab7d6e..20e24d5 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -35,6 +35,8 @@ =20 typedef struct DisasContext { struct TranslationBlock *tb; + TCGv *gregs; /* active bank */ + TCGv *altregs; /* inactive, alternate, bank */ target_ulong pc; uint16_t opcode; uint32_t tbflags; /* should stay unmodified during the TB translati= on */ @@ -64,7 +66,7 @@ enum { =20 /* global register indexes */ static TCGv_env cpu_env; -static TCGv cpu_gregs[24]; +static TCGv cpu_gregs[2][16]; static TCGv cpu_sr, cpu_sr_m, cpu_sr_q, cpu_sr_t; static TCGv cpu_pc, cpu_ssr, cpu_spc, cpu_gbr; static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl; @@ -99,16 +101,31 @@ void sh4_translate_init(void) "FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1", }; =20 - if (done_init) + if (done_init) { return; + } =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); tcg_ctx.tcg_env =3D cpu_env; =20 - for (i =3D 0; i < 24; i++) - cpu_gregs[i] =3D tcg_global_mem_new_i32(cpu_env, - offsetof(CPUSH4State, gregs[= i]), - gregnames[i]); + for (i =3D 0; i < 8; i++) { + cpu_gregs[0][i] + =3D tcg_global_mem_new_i32(cpu_env, + offsetof(CPUSH4State, gregs[i]), + gregnames[i]); + } + for (i =3D 8; i < 16; i++) { + cpu_gregs[0][i] =3D cpu_gregs[1][i] + =3D tcg_global_mem_new_i32(cpu_env, + offsetof(CPUSH4State, gregs[i]), + gregnames[i]); + } + for (i =3D 16; i < 24; i++) { + cpu_gregs[1][i - 16] + =3D tcg_global_mem_new_i32(cpu_env, + offsetof(CPUSH4State, gregs[i]), + gregnames[i]); + } =20 cpu_pc =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUSH4State, pc), "PC"); @@ -362,13 +379,8 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int re= g) #define B11_8 ((ctx->opcode >> 8) & 0xf) #define B15_12 ((ctx->opcode >> 12) & 0xf) =20 -#define REG(x) ((x) < 8 && (ctx->tbflags & (1u << SR_MD))\ - && (ctx->tbflags & (1u << SR_RB))\ - ? (cpu_gregs[x + 16]) : (cpu_gregs[x])) - -#define ALTREG(x) ((x) < 8 && (!(ctx->tbflags & (1u << SR_MD))\ - || !(ctx->tbflags & (1u << SR_RB)))\ - ? (cpu_gregs[x + 16]) : (cpu_gregs[x])) +#define REG(x) ctx->gregs[x] +#define ALTREG(x) ctx->altregs[x] =20 #define FREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)) #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) @@ -2214,6 +2226,7 @@ void gen_intermediate_code(CPUSH4State * env, struct = TranslationBlock *tb) target_ulong pc_start; int num_insns; int max_insns; + int bank; =20 pc_start =3D tb->pc; ctx.pc =3D pc_start; @@ -2229,6 +2242,10 @@ void gen_intermediate_code(CPUSH4State * env, struct= TranslationBlock *tb) ctx.features =3D env->features; ctx.has_movcal =3D (ctx.tbflags & TB_FLAG_PENDING_MOVCA); =20 + bank =3D (ctx.tbflags & (1 << SR_MD)) && (ctx.tbflags & (1 << SR_RB)); + ctx.gregs =3D cpu_gregs[bank]; + ctx.altregs =3D cpu_gregs[bank ^ 1]; + max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; --=20 2.9.4