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[66.91.136.156]) by smtp.gmail.com with ESMTPSA id u85sm371825qku.42.2017.07.05.17.24.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Jul 2017 17:24:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=ep4es793wXbFPhzqDI4BTeE541BKnHdvpWGJ4L+4VSI=; b=N/MRRMHw4VXvhW1QqYW734k81dE37kqdYAWikVPJbwWVE9uCeFjx+4kEywHpmpvnKg AgvviMQB2JI11Qmm2YN4F8d8bT7ThxvmCF4PXJN/q9NXgPPPRsbvRFUuP7OK53/1Ej7g iFj7Lk46up+47fhQ3QnG2JmCmY1AjhXH0XXDjiNuNA9uP9AaiyJGDLx7b2eJ8W2Q5JzP lr5cIZMgIZWRF96978GIUMROoQ+v0V61R9Z8V7vfaQM9A0Q6jOtAqcNlOZ4TGaiOxwqV lD3FWIF2dag7/46CAkWC9pMHmPfXXMKoOuaxqqZtHdn3FJKLy677CNvhP6dI6CE9H8KT FWoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=ep4es793wXbFPhzqDI4BTeE541BKnHdvpWGJ4L+4VSI=; b=brcapKB42CCGMHffTgEmmwSePbXUvcr7PBHdy64/Du3hgQivCzj/VED148PUF16ISM KI4LG0cBVWKJLeMoBfwpJ4TY4CFbeA46KTc2w7KmRk94SMZbevWFIa7EB74y5ahJ4GJd LcuGgLATBxug8xUsmgkS5LXeeDgQ7VA1ZfcptSpgnyfrKbLXL7rChr/VW+NPFHopKIkM OKHwH8XOwwz36j9OfTLZfhSdu8kgenzphtCKH1V+8BFlTOwE/asQW2j8s9gbbM5qWWFk RTvPHlCP3ykjeR4pV/ix0g1AtV1pc83kZov0PAWmApYMyx6oWn6XRBRacylTFa/L6MkD sIig== X-Gm-Message-State: AIVw1119iCAVpbo3YUWHcsWrZ7+ZoRMBggblHSSxGasKSe+8aZViR4vg bYjYG0si3zs6RP+TTmg= X-Received: by 10.237.54.42 with SMTP id e39mr21614097qtb.30.1499300662803; Wed, 05 Jul 2017 17:24:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 5 Jul 2017 14:23:51 -1000 Message-Id: <20170706002401.10507-2-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170706002401.10507-1-rth@twiddle.net> References: <20170706002401.10507-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::244 Subject: [Qemu-devel] [PATCH 01/11] target/sh4: Use cmpxchg for movco X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno@clisp.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" As for other targets, cmpxchg isn't quite right for ll/sc, suffering from an ABA race, but is sufficient to implement portable atomic operations. Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 3 ++- target/sh4/translate.c | 56 +++++++++++++++++++++++++++++++++-------------= ---- 2 files changed, 39 insertions(+), 20 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index ffb9168..b15116e 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -169,7 +169,8 @@ typedef struct CPUSH4State { tlb_t itlb[ITLB_SIZE]; /* instruction translation table */ tlb_t utlb[UTLB_SIZE]; /* unified translation table */ =20 - uint32_t ldst; + uint32_t lock_addr; + uint32_t lock_value; =20 /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 8bc132b..6b247fa 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -68,7 +68,8 @@ static TCGv cpu_gregs[24]; static TCGv cpu_sr, cpu_sr_m, cpu_sr_q, cpu_sr_t; static TCGv cpu_pc, cpu_ssr, cpu_spc, cpu_gbr; static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl; -static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_ldst; +static TCGv cpu_pr, cpu_fpscr, cpu_fpul; +static TCGv cpu_lock_addr, cpu_lock_value; static TCGv cpu_fregs[32]; =20 /* internal register indexes */ @@ -151,8 +152,12 @@ void sh4_translate_init(void) offsetof(CPUSH4State, delayed_cond), "_delayed_cond_"); - cpu_ldst =3D tcg_global_mem_new_i32(cpu_env, - offsetof(CPUSH4State, ldst), "_ldst_"); + cpu_lock_addr =3D tcg_global_mem_new_i32(cpu_env, + offsetof(CPUSH4State, lock_addr), + "_lock_addr_"); + cpu_lock_value =3D tcg_global_mem_new_i32(cpu_env, + offsetof(CPUSH4State, lock_value), + "_lock_value_"); =20 for (i =3D 0; i < 32; i++) cpu_fregs[i] =3D tcg_global_mem_new_i32(cpu_env, @@ -1526,20 +1531,32 @@ static void _decode_opc(DisasContext * ctx) return; case 0x0073: /* MOVCO.L - LDST -> T + LDST -> T If (T =3D=3D 1) R0 -> (Rn) 0 -> LDST */ if (ctx->features & SH_FEATURE_SH4A) { - TCGLabel *label =3D gen_new_label(); - tcg_gen_mov_i32(cpu_sr_t, cpu_ldst); - tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label); - tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL); - gen_set_label(label); - tcg_gen_movi_i32(cpu_ldst, 0); - return; - } else - break; + TCGLabel *fail =3D gen_new_label(); + TCGLabel *done =3D gen_new_label(); + TCGv tmp; + + tcg_gen_brcond_i32(TCG_COND_NE, REG(B11_8), cpu_lock_addr, fai= l); + + tmp =3D tcg_temp_new(); + tcg_gen_atomic_cmpxchg_i32(tmp, REG(B11_8), cpu_lock_value, + REG(0), ctx->memidx, MO_TEUL); + tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_t, tmp, cpu_lock_value= ); + tcg_temp_free(tmp); + tcg_gen_br(done); + + gen_set_label(fail); + tcg_gen_movi_i32(cpu_sr_t, 0); + + gen_set_label(done); + return; + } else { + break; + } case 0x0063: /* MOVLI.L @Rm,R0 1 -> LDST @@ -1547,13 +1564,14 @@ static void _decode_opc(DisasContext * ctx) When interrupt/exception occurred 0 -> LDST */ - if (ctx->features & SH_FEATURE_SH4A) { - tcg_gen_movi_i32(cpu_ldst, 0); + if (ctx->features & SH_FEATURE_SH4A) { tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL); - tcg_gen_movi_i32(cpu_ldst, 1); - return; - } else - break; + tcg_gen_mov_i32(cpu_lock_addr, REG(B11_8)); + tcg_gen_mov_i32(cpu_lock_value, REG(0)); + return; + } else { + break; + } case 0x0093: /* ocbi @Rn */ { gen_helper_ocbi(cpu_env, REG(B11_8)); --=20 2.9.4 From nobody Wed Nov 5 08:02:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499301022661426.8971488325657; Wed, 5 Jul 2017 17:30:22 -0700 (PDT) Received: from localhost ([::1]:48649 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSugW-0004A7-7L for importer@patchew.org; Wed, 05 Jul 2017 20:30:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59603) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSuaq-0007Pj-BM for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSuap-0002Mb-A5 for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:28 -0400 Received: from mail-qt0-x244.google.com ([2607:f8b0:400d:c0d::244]:33869) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dSuap-0002MW-5m for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:27 -0400 Received: by mail-qt0-x244.google.com with SMTP id m54so645233qtb.1 for ; Wed, 05 Jul 2017 17:24:27 -0700 (PDT) Received: from bigtime.twiddle.net.com (rrcs-66-91-136-156.west.biz.rr.com. [66.91.136.156]) by smtp.gmail.com with ESMTPSA id u85sm371825qku.42.2017.07.05.17.24.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Jul 2017 17:24:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=KdxOpIn7expYDVmuToYLNLB06Cj4xS3Ky//rBKQoVBo=; b=YAzz8NGDapL62Y2so3A/iRR+eVzFBi4h3d/HAtML20YftYk55Z/rJDjBH0wqDUDnr3 HD+S2GHBRPFaGBCgwOMZeT9gHrAhjfQKDhssMVXgNpq7CCp38TUQwAepd+n9PjlC+NOx /mPyjp0eFtNtNuXAZkubWTbxVqcdPvzSx2DwWvqDrmMyAHpb4SOlqlLM7LYg8pTc6Bmm FHy1s197sRs0jABt/dJDxzmYxVkO9E0Yo+8CWvgGPi8GOMBB0Y48gAcK12moiMOwEt6J enSdKqHGkToXe7TpYW/piLeR3gDZolaSA3WKHHDgL9boT5lpBCSTtW7WDWVgCI8JWHzG PiZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=KdxOpIn7expYDVmuToYLNLB06Cj4xS3Ky//rBKQoVBo=; b=EmX2y7beRuubsKn178capJmZPsjKC/DPZWxNoXzs1doU30DlBpchzMdLTWk1FSHOnU SvGh512hPBP9377tVquucTIFloDnmXJD20GXIg11jOspFN5P3kr1RiZsv1U0yB/OSmW6 s9hDBEEn8SFXgT0Tu7+kkzt9GsyVXGPn4fp/2FeZcO0bd/49PZWHo97rPPSFEGj1ErdM pVXL33PaAvBtdjw/RNJ+Q47F2FhRU5VO5JED0rxNpyGYCJ3tUAra/3MxavqXvPXtFecI 7vR95IuTVcCu+rnAOjkobcfklk3HSt0lFNeFcfM2YF3ZbutD3fGtnO30AJdEXAtbm2EC aniA== X-Gm-Message-State: AKS2vOySWMegupPEqO7hOF9HkaFLNNY95XU9jiwLGXHqUFR+iobtroBR 96QReAJZ7JI3PGtrsPg= X-Received: by 10.200.48.38 with SMTP id f35mr56928196qte.88.1499300666553; Wed, 05 Jul 2017 17:24:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 5 Jul 2017 14:23:52 -1000 Message-Id: <20170706002401.10507-3-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170706002401.10507-1-rth@twiddle.net> References: <20170706002401.10507-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::244 Subject: [Qemu-devel] [PATCH 02/11] target/sh4: Consolidate end-of-TB tests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno@clisp.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We can fold 3 different tests within the decode loop into a more accurate computation of max_insns to start. Signed-off-by: Richard Henderson Reviewed-by: Aurelien Jarno --- target/sh4/translate.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 6b247fa..e1661e9 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1856,7 +1856,6 @@ void gen_intermediate_code(CPUSH4State * env, struct = TranslationBlock *tb) ctx.features =3D env->features; ctx.has_movcal =3D (ctx.tbflags & TB_FLAG_PENDING_MOVCA); =20 - num_insns =3D 0; max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -1864,9 +1863,23 @@ void gen_intermediate_code(CPUSH4State * env, struct= TranslationBlock *tb) if (max_insns > TCG_MAX_INSNS) { max_insns =3D TCG_MAX_INSNS; } + /* Since the ISA is fixed-width, we can bound by the number + of instructions remaining on the page. */ + num_insns =3D (TARGET_PAGE_SIZE - (ctx.pc & (TARGET_PAGE_SIZE - 1))) /= 2; + if (max_insns > num_insns) { + max_insns =3D num_insns; + } + /* Single stepping means just that. */ + if (ctx.singlestep_enabled || singlestep) { + max_insns =3D 1; + } =20 gen_tb_start(tb); - while (ctx.bstate =3D=3D BS_NONE && !tcg_op_buf_full()) { + num_insns =3D 0; + + while (ctx.bstate =3D=3D BS_NONE + && num_insns < max_insns + && !tcg_op_buf_full()) { tcg_gen_insn_start(ctx.pc, ctx.envflags); num_insns++; =20 @@ -1890,18 +1903,10 @@ void gen_intermediate_code(CPUSH4State * env, struc= t TranslationBlock *tb) ctx.opcode =3D cpu_lduw_code(env, ctx.pc); decode_opc(&ctx); ctx.pc +=3D 2; - if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) =3D=3D 0) - break; - if (cs->singlestep_enabled) { - break; - } - if (num_insns >=3D max_insns) - break; - if (singlestep) - break; } - if (tb->cflags & CF_LAST_IO) + if (tb->cflags & CF_LAST_IO) { gen_io_end(); + } if (cs->singlestep_enabled) { gen_save_cpu_state(&ctx, true); gen_helper_debug(cpu_env); --=20 2.9.4 From nobody Wed Nov 5 08:02:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499300790897702.3903273706393; Wed, 5 Jul 2017 17:26:30 -0700 (PDT) Received: from localhost ([::1]:48635 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSucn-0000J3-Dg for importer@patchew.org; Wed, 05 Jul 2017 20:26:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59672) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSuaw-0007Th-HP for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSuat-0002O0-9V for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:34 -0400 Received: from mail-qt0-x244.google.com ([2607:f8b0:400d:c0d::244]:34880) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dSuat-0002Nt-4F for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:31 -0400 Received: by mail-qt0-x244.google.com with SMTP id w12so640012qta.2 for ; Wed, 05 Jul 2017 17:24:31 -0700 (PDT) Received: from bigtime.twiddle.net.com (rrcs-66-91-136-156.west.biz.rr.com. [66.91.136.156]) by smtp.gmail.com with ESMTPSA id u85sm371825qku.42.2017.07.05.17.24.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Jul 2017 17:24:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=GBD0NlaQS8q+wm8Vco3O14v78ntisuIaEOEMoyCYoMA=; b=ljKdddGGedVE85fzfJ5I8erz/DDnqyWZXq//px47oL6ZzTcBZxfiE1sxs49Nf3BoLq BD4YxRFe1s8rnKqAakKhSeQS0cI2Qah0qXmujc/9yIiDzhX19+mNPAxAJgFfUSNzgbhq RAtEOccNPqoj7f4iSz6dyq6zNTMcUplVXdz8m7XobK1aK+8XKro4SU+Tkzq8TCOQIQ/6 7WG7r8m2XI0e2aJEE/MboMf++82f219fdCezn7neI157kDMXykNtgKVk101GQdj+sJ9p 2vsTXd5vSwPGdj2Gl1PtUnvXgt8LwnitRjzSQqaNO98d5zUqFH3sMO/JYlJ+lbQb8TET QZEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=GBD0NlaQS8q+wm8Vco3O14v78ntisuIaEOEMoyCYoMA=; b=h39tS499iHwmAs9JfH8dU25ueZfpTuy6RXMTx2fLcsLIrcDy9jd176hlxNY29vSHXD kN0qo153vXA+3Qv+XX/EQt6kNWX/gZojgAboqCpsN7Cq8nDKh9NhRheLc/2I/lOIF/W5 woPNwun7watjvlR0ETdzICGCmTeV3nwIDnngGbw9ksuH1CTacSk2FEGP0i9rE1BSXr+k Gxii3r6cJQl8Qxqax4hCxW1fpB/6Aap3R1EGY34GRwSa224fMP/39CUSsneXIo0Fz7GS HvWPyAMDvdPbeOY+HFBLfBoRX9jZ4TYqkhcDz0Lk13ESFMcPN7xsiFzjHImANgHJ71fb JIig== X-Gm-Message-State: AIVw111glU4C8US3JRdjnIxe5gWKxJvLU4iECLz4Ao4u2Nftn7Jkx5yg faKBjyqdkCvFkCDDiOs= X-Received: by 10.237.44.225 with SMTP id g88mr6692671qtd.150.1499300670306; Wed, 05 Jul 2017 17:24:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 5 Jul 2017 14:23:53 -1000 Message-Id: <20170706002401.10507-4-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170706002401.10507-1-rth@twiddle.net> References: <20170706002401.10507-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::244 Subject: [Qemu-devel] [PATCH 03/11] target/sh4: Handle user-space atomics X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno@clisp.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For uniprocessors, SH4 uses optimistic restartable atomic sequences. Upon an interrupt, a real kernel would simply notice magic values in the registers and reset the PC to the start of the sequence. For QEMU, we cannot do this in quite the same way. Instead, we notice the normal start of such a sequence (mov #-x,r15), and start a new TB that can be executed under cpu_exec_step_atomic. Reported-by: Bruno Haible LP: https://bugs.launchpad.net/bugs/1701971 Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 21 ++++++-- target/sh4/helper.h | 1 + target/sh4/op_helper.c | 6 +++ target/sh4/translate.c | 137 +++++++++++++++++++++++++++++++++++++++++++--= ---- 4 files changed, 147 insertions(+), 18 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index b15116e..0a08b12 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -96,6 +96,12 @@ #define DELAY_SLOT_CONDITIONAL (1 << 1) #define DELAY_SLOT_RTE (1 << 2) =20 +#define TB_FLAG_PENDING_MOVCA (1 << 3) + +#define GUSA_SHIFT 4 +#define GUSA_EXCLUSIVE (1 << 12) +#define GUSA_MASK ((0xff << GUSA_SHIFT) | GUSA_EXCLUSIVE) + typedef struct tlb_t { uint32_t vpn; /* virtual page number */ uint32_t ppn; /* physical page number */ @@ -367,7 +373,11 @@ static inline int cpu_ptel_pr (uint32_t ptel) #define PTEA_TC (1 << 3) #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3) =20 -#define TB_FLAG_PENDING_MOVCA (1 << 4) +#ifdef CONFIG_USER_ONLY +#define TB_FLAG_ENVFLAGS_MASK (DELAY_SLOT_MASK | GUSA_MASK) +#else +#define TB_FLAG_ENVFLAGS_MASK DELAY_SLOT_MASK +#endif =20 static inline target_ulong cpu_read_sr(CPUSH4State *env) { @@ -388,12 +398,17 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *= env, target_ulong *pc, target_ulong *cs_base, uint32_t *f= lags) { *pc =3D env->pc; +#ifdef CONFIG_USER_ONLY + /* For a gUSA region, notice the end of the region. */ + *cs_base =3D env->flags & GUSA_MASK ? env->gregs[0] : 0; +#else *cs_base =3D 0; - *flags =3D (env->flags & DELAY_SLOT_MASK) /* Bits = 0- 2 */ +#endif + *flags =3D env->flags /* TB_FLAG_ENVFLAGS_MASK: bits 0-2, 4-12 */ | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-= 21 */ | (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-= 30 */ | (env->sr & (1u << SR_FD)) /* Bit 15 */ - | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */ + | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ } =20 #endif /* SH4_CPU_H */ diff --git a/target/sh4/helper.h b/target/sh4/helper.h index dce859c..efbb560 100644 --- a/target/sh4/helper.h +++ b/target/sh4/helper.h @@ -6,6 +6,7 @@ DEF_HELPER_1(raise_slot_fpu_disable, noreturn, env) DEF_HELPER_1(debug, noreturn, env) DEF_HELPER_1(sleep, noreturn, env) DEF_HELPER_2(trapa, noreturn, env, i32) +DEF_HELPER_1(exclusive, noreturn, env) =20 DEF_HELPER_3(movcal, void, env, i32, i32) DEF_HELPER_1(discard_movcal_backup, void, env) diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 528a40a..3139ad2 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -115,6 +115,12 @@ void helper_trapa(CPUSH4State *env, uint32_t tra) raise_exception(env, 0x160, 0); } =20 +void helper_exclusive(CPUSH4State *env) +{ + /* We do not want cpu_restore_state to run. */ + cpu_loop_exit_atomic(ENV_GET_CPU(env), 0); +} + void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value) { if (cpu_sh4_is_cached (env, address)) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index e1661e9..02c6efc 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -225,7 +225,7 @@ static inline void gen_save_cpu_state(DisasContext *ctx= , bool save_pc) if (ctx->delayed_pc !=3D (uint32_t) -1) { tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc); } - if ((ctx->tbflags & DELAY_SLOT_MASK) !=3D ctx->envflags) { + if ((ctx->tbflags & TB_FLAG_ENVFLAGS_MASK) !=3D ctx->envflags) { tcg_gen_movi_i32(cpu_flags, ctx->envflags); } } @@ -239,7 +239,7 @@ static inline bool use_goto_tb(DisasContext *ctx, targe= t_ulong dest) #ifndef CONFIG_USER_ONLY return (ctx->tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_MAS= K); #else - return true; + return (ctx->tbflags & GUSA_EXCLUSIVE) =3D=3D 0; #endif } =20 @@ -260,16 +260,17 @@ static void gen_goto_tb(DisasContext *ctx, int n, tar= get_ulong dest) =20 static void gen_jump(DisasContext * ctx) { - if (ctx->delayed_pc =3D=3D (uint32_t) - 1) { - /* Target is not statically known, it comes necessarily from a - delayed jump as immediate jump are conditinal jumps */ - tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc); + if (ctx->delayed_pc =3D=3D -1) { + /* Target is not statically known, it comes necessarily from a + delayed jump as immediate jump are conditinal jumps */ + tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc); tcg_gen_discard_i32(cpu_delayed_pc); - if (ctx->singlestep_enabled) + if (ctx->singlestep_enabled) { gen_helper_debug(cpu_env); - tcg_gen_exit_tb(0); + } + tcg_gen_exit_tb(0); } else { - gen_goto_tb(ctx, 0, ctx->delayed_pc); + gen_goto_tb(ctx, 0, ctx->delayed_pc); } } =20 @@ -278,6 +279,30 @@ static void gen_conditional_jump(DisasContext * ctx, target_ulong ift, target_ulong ifnott) { TCGLabel *l1 =3D gen_new_label(); + +#ifdef CONFIG_USER_ONLY + if (ctx->tbflags & GUSA_EXCLUSIVE) { + /* When in an exclusive region, we must continue to the end. + Therefore, exit the region on a taken branch, but otherwise + fall through to the next instruction. */ + uint32_t taken; + TCGCond cond; + + if (ift =3D=3D ctx->pc + 2) { + taken =3D ifnott; + cond =3D TCG_COND_NE; + } else { + taken =3D ift; + cond =3D TCG_COND_EQ; + } + tcg_gen_brcondi_i32(cond, cpu_sr_t, 0, l1); + tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~GUSA_MASK); + gen_goto_tb(ctx, 0, taken); + gen_set_label(l1); + return; + } +#endif + gen_save_cpu_state(ctx, false); tcg_gen_brcondi_i32(TCG_COND_NE, cpu_sr_t, 0, l1); gen_goto_tb(ctx, 0, ifnott); @@ -289,13 +314,28 @@ static void gen_conditional_jump(DisasContext * ctx, /* Delayed conditional jump (bt or bf) */ static void gen_delayed_conditional_jump(DisasContext * ctx) { - TCGLabel *l1; - TCGv ds; + TCGLabel *l1 =3D gen_new_label(); + TCGv ds =3D tcg_temp_new(); =20 - l1 =3D gen_new_label(); - ds =3D tcg_temp_new(); tcg_gen_mov_i32(ds, cpu_delayed_cond); tcg_gen_discard_i32(cpu_delayed_cond); + +#ifdef CONFIG_USER_ONLY + if (ctx->tbflags & GUSA_EXCLUSIVE) { + /* When in an exclusive region, we must continue to the end. + Therefore, exit the region on a taken branch, but otherwise + fall through to the next instruction. */ + tcg_gen_brcondi_i32(TCG_COND_EQ, ds, 0, l1); + + /* Leave the gUSA region. */ + tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~GUSA_MASK); + gen_jump(ctx); + + gen_set_label(l1); + return; + } +#endif + tcg_gen_brcondi_i32(TCG_COND_NE, ds, 0, l1); gen_goto_tb(ctx, 1, ctx->pc + 2); gen_set_label(l1); @@ -480,6 +520,15 @@ static void _decode_opc(DisasContext * ctx) } return; case 0xe000: /* mov #imm,Rn */ +#ifdef CONFIG_USER_ONLY + /* Detect the start of a gUSA region. If so, update envflags + and end the TB. This will allow us to see the end of the + region (stored in R0) in the next TB. */ + if (B11_8 =3D=3D 15 && B7_0s < 0) { + ctx->envflags =3D deposit32(ctx->envflags, GUSA_SHIFT, 8, B7_0= s); + ctx->bstate =3D BS_STOP; + } +#endif tcg_gen_movi_i32(REG(B11_8), B7_0s); return; case 0x9000: /* mov.w @(disp,PC),Rn */ @@ -1822,6 +1871,20 @@ static void decode_opc(DisasContext * ctx) if (old_flags & DELAY_SLOT_MASK) { /* go out of the delay slot */ ctx->envflags &=3D ~DELAY_SLOT_MASK; + +#ifdef CONFIG_USER_ONLY + /* When in an exclusive region, we must continue to the end + for conditional branches. */ + if (ctx->tbflags & GUSA_EXCLUSIVE + && old_flags & DELAY_SLOT_CONDITIONAL) { + gen_delayed_conditional_jump(ctx); + return; + } + /* Otherwise this is probably an invalid gUSA region. + Drop the GUSA bits so the next TB doesn't see them. */ + ctx->envflags &=3D ~GUSA_MASK; +#endif + tcg_gen_movi_i32(cpu_flags, ctx->envflags); ctx->bstate =3D BS_BRANCH; if (old_flags & DELAY_SLOT_CONDITIONAL) { @@ -1829,10 +1892,35 @@ static void decode_opc(DisasContext * ctx) } else { gen_jump(ctx); } - } } =20 +#ifdef CONFIG_USER_ONLY +static int decode_gusa(DisasContext *ctx) +{ + uint32_t pc =3D ctx->pc; + uint32_t pc_end =3D ctx->tb->cs_base; + + qemu_log_mask(LOG_UNIMP, "Unrecognized gUSA sequence %08x-%08x\n", + pc, pc_end); + + /* Restart with the EXCLUSIVE bit set, within a TB run via + cpu_exec_step_atomic holding the exclusive lock. */ + tcg_gen_insn_start(pc, ctx->envflags); + ctx->envflags |=3D GUSA_EXCLUSIVE; + gen_save_cpu_state(ctx, false); + gen_helper_exclusive(cpu_env); + ctx->bstate =3D BS_EXCP; + + /* We're not executing an instruction, but we must report one for the + purposes of accounting within the TB. At which point we might as + well report the entire region so that it's immediately available + in the disassembly dump. */ + ctx->pc =3D pc_end; + return 1; +} +#endif + void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb) { SuperHCPU *cpu =3D sh_env_get_cpu(env); @@ -1845,7 +1933,7 @@ void gen_intermediate_code(CPUSH4State * env, struct = TranslationBlock *tb) pc_start =3D tb->pc; ctx.pc =3D pc_start; ctx.tbflags =3D (uint32_t)tb->flags; - ctx.envflags =3D tb->flags & DELAY_SLOT_MASK; + ctx.envflags =3D tb->flags & TB_FLAG_ENVFLAGS_MASK; ctx.bstate =3D BS_NONE; ctx.memidx =3D (ctx.tbflags & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; /* We don't know if the delayed pc came from a dynamic or static branc= h, @@ -1877,6 +1965,17 @@ void gen_intermediate_code(CPUSH4State * env, struct= TranslationBlock *tb) gen_tb_start(tb); num_insns =3D 0; =20 +#ifdef CONFIG_USER_ONLY + if (ctx.tbflags & GUSA_EXCLUSIVE) { + /* Regardless of single-stepping or the end of the page, + we must complete execution of the gUSA region while + holding the exclusive lock. */ + max_insns =3D (tb->cs_base - ctx.pc) / 2; + } else if (ctx.tbflags & GUSA_MASK) { + num_insns =3D decode_gusa(&ctx); + } +#endif + while (ctx.bstate =3D=3D BS_NONE && num_insns < max_insns && !tcg_op_buf_full()) { @@ -1907,6 +2006,14 @@ void gen_intermediate_code(CPUSH4State * env, struct= TranslationBlock *tb) if (tb->cflags & CF_LAST_IO) { gen_io_end(); } + +#ifdef CONFIG_USER_ONLY + if ((ctx.tbflags & GUSA_EXCLUSIVE) && ctx.bstate =3D=3D BS_NONE) { + /* Ending the region of exclusivity. Clear the bits. */ + ctx.envflags &=3D ~GUSA_MASK; + } +#endif + if (cs->singlestep_enabled) { gen_save_cpu_state(&ctx, true); gen_helper_debug(cpu_env); --=20 2.9.4 From nobody Wed Nov 5 08:02:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149930092422548.016328831721125; Wed, 5 Jul 2017 17:28:44 -0700 (PDT) Received: from localhost ([::1]:48642 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSuex-0002At-1u for importer@patchew.org; Wed, 05 Jul 2017 20:28:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59698) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSuay-0007V5-Vd for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSuax-0002PZ-7V for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:36 -0400 Received: from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:35760) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dSuax-0002PO-1q for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:35 -0400 Received: by mail-qk0-x243.google.com with SMTP id 16so647348qkg.2 for ; Wed, 05 Jul 2017 17:24:35 -0700 (PDT) Received: from bigtime.twiddle.net.com (rrcs-66-91-136-156.west.biz.rr.com. [66.91.136.156]) by smtp.gmail.com with ESMTPSA id u85sm371825qku.42.2017.07.05.17.24.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Jul 2017 17:24:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=WXdwifL93X0z4n54qawmHFEVY2bx1xK1JAIRcet8xwc=; b=caDFbCUXF5vVqHJgjOzKD3mfdAaIqVctepcT50MD7CSEZgByURzYaE1JtzKskcYiwL UpiuNG5kjPDYXzhplf8i7vv7KuhLJKIGS++PYAwmw3eRtexFQmVcRgidE8P1hTovcaNw IEKQ+taTSxnegT+U+XipRssJ2bD5woIAgyFxrTFloLw+R417bJpjj+qXoIhZPI3HzYzF OEhcEi1LmpJgt1yCq1/UeS+VK+2YTdKyLxh5jf6uKbIQ4VFQKdJRMWTLFh0nnmaLWJZN UrQjcTDujxzOKswPoKTqDQ8CVHV88MYhU1Lp7ItXMU3l8IP/u0mMejjgWr6M4V2pS4fB eAKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=WXdwifL93X0z4n54qawmHFEVY2bx1xK1JAIRcet8xwc=; b=W02FQ2ol+fWpOE9t0jCbDhDk1uEG6ypBhS/kMh2LvNEZatVqe45cAvD6IFrNeVdpcN tVisj4xyZ3IdB/1PP7gxomb5zqQDXD5bM7esGwy579xZT0sjE/tMTTlEmCavYwu5P9qa i8+Cza9ea/pDjhvpgBEWj2jj8MQvZeuJ/Z5GMTrX5Rz6dIMGbmrNYr2CGKXcC/byiOVC wE9uptFJhVLea3a4QKw7VsAsW3uxzSmC1jlklG70cwsyYMLVIfaq24rrKI7QuD3O7y1c jhJHOsG+t2a1SBw2Q+7maBY66+lRePev1ChNzA+gn3Z/ms1h44d6JWdDc06g1Y1kSgTW lrTw== X-Gm-Message-State: AKS2vOw4m8/+GNqVcKVReSLtEQxlN3EKKMSUh0EbbjTKrR2OX6athSFr w14qWtYYKOmb2I0Q3Ys= X-Received: by 10.55.22.71 with SMTP id g68mr59120979qkh.218.1499300674033; Wed, 05 Jul 2017 17:24:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 5 Jul 2017 14:23:54 -1000 Message-Id: <20170706002401.10507-5-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170706002401.10507-1-rth@twiddle.net> References: <20170706002401.10507-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH 04/11] target/sh4: Recognize common gUSA sequences X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno@clisp.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For many of the sequences produced by gcc or glibc, we can translate these as host atomic operations. Which saves the need to acquire the exclusive lock. Signed-off-by: Richard Henderson --- target/sh4/translate.c | 300 +++++++++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 290 insertions(+), 10 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 02c6efc..9ab7d6e 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1896,11 +1896,296 @@ static void decode_opc(DisasContext * ctx) } =20 #ifdef CONFIG_USER_ONLY -static int decode_gusa(DisasContext *ctx) +/* For uniprocessors, SH4 uses optimistic restartable atomic sequences. + Upon an interrupt, a real kernel would simply notice magic values in + the registers and reset the PC to the start of the sequence. + + For QEMU, we cannot do this in quite the same way. Instead, we notice + the normal start of such a sequence (mov #-x,r15). While we can handle + any sequence via cpu_exec_step_atomic, we can recognize the "normal" + sequences and transform them into atomic operations as seen by the host. +*/ +static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insn= s) { + uint16_t insns[5]; + int ld_adr, ld_reg, ld_mop; + int op_reg, op_arg, op_opc; + int mt_reg, st_reg, st_mop; + uint32_t pc =3D ctx->pc; uint32_t pc_end =3D ctx->tb->cs_base; + int backup =3D sextract32(ctx->tbflags, GUSA_SHIFT, 8); + int max_insns =3D (pc_end - pc) / 2; + int i; + + if (pc !=3D pc_end + backup || max_insns < 2) { + /* This is a malformed gUSA region. Don't do anything special, + since the interpreter is likely to get confused. */ + ctx->envflags &=3D ~GUSA_MASK; + return 0; + } + + if (ctx->tbflags & GUSA_EXCLUSIVE) { + /* Regardless of single-stepping or the end of the page, + we must complete execution of the gUSA region while + holding the exclusive lock. */ + *pmax_insns =3D max_insns; + return 0; + } + + /* The state machine below will consume only a few insns. + If there are more than that in a region, fail now. */ + if (max_insns > ARRAY_SIZE(insns)) { + goto fail; + } + + /* Read all of the insns for the region. */ + for (i =3D 0; i < max_insns; ++i) { + insns[i] =3D cpu_lduw_code(env, pc + i * 2); + } + + ld_adr =3D ld_reg =3D ld_mop =3D -1; + op_reg =3D op_arg =3D op_opc =3D -1; + mt_reg =3D -1; + st_reg =3D st_mop =3D -1; + i =3D 0; + +#define NEXT_INSN \ + do { if (i >=3D max_insns) goto fail; ctx->opcode =3D insns[i++]; } wh= ile (0) + + /* + * Expect a load to begin the region. + */ + NEXT_INSN; + switch (ctx->opcode & 0xf00f) { + case 0x6000: /* mov.b @Rm,Rn */ + ld_mop =3D MO_SB; + break; + case 0x6001: /* mov.w @Rm,Rn */ + ld_mop =3D MO_TESW; + break; + case 0x6002: /* mov.l @Rm,Rn */ + ld_mop =3D MO_TESL; + break; + default: + goto fail; + } + ld_adr =3D B7_4; + op_reg =3D ld_reg =3D B11_8; + if (ld_adr =3D=3D ld_reg) { + goto fail; + } + + /* + * Expect an optional register move. + */ + NEXT_INSN; + switch (ctx->opcode & 0xf00f) { + case 0x6003: /* mov Rm,Rn */ + /* Here we want to recognize the ld output being + saved for later consumtion (e.g. atomic_fetch_op). */ + if (ld_reg !=3D B7_4) { + goto fail; + } + op_reg =3D B11_8; + break; + + default: + /* Put back and re-examine as operation. */ + --i; + } + + /* + * Expect the operation. + */ + NEXT_INSN; + switch (ctx->opcode & 0xf00f) { + case 0x300c: /* add Rm,Rn */ + op_opc =3D INDEX_op_add_i32; + goto do_reg_op; + case 0x2009: /* and Rm,Rn */ + op_opc =3D INDEX_op_and_i32; + goto do_reg_op; + case 0x200a: /* xor Rm,Rn */ + op_opc =3D INDEX_op_xor_i32; + goto do_reg_op; + case 0x200b: /* or Rm,Rn */ + op_opc =3D INDEX_op_or_i32; + do_reg_op: + /* The operation register should be as expected, and the + other input cannot depend on the load. */ + op_arg =3D B7_4; + if (op_reg !=3D B11_8 || op_arg =3D=3D op_reg || op_arg =3D=3D ld_= reg) { + goto fail; + } + break; + + case 0x3000: /* cmp/eq Rm,Rn */ + /* Looking for the middle of a compare-and-swap sequence, + beginning with the compare. Operands can be either order, + but with only one overlapping the load. */ + if ((op_reg =3D=3D B11_8) + (op_reg =3D=3D B7_4) !=3D 1) { + goto fail; + } + op_opc =3D INDEX_op_setcond_i32; /* placeholder */ + op_arg =3D (op_reg =3D=3D B11_8 ? B7_4 : B11_8); + + NEXT_INSN; + switch (ctx->opcode & 0xff00) { + case 0x8b00: /* bf label */ + case 0x8f00: /* bf/s label */ + if (pc + (i + 1 + B7_0s) * 2 !=3D pc_end) { + goto fail; + } + if ((ctx->opcode & 0xff00) =3D=3D 0x8b00) { /* bf label */ + break; + } + /* We're looking to unconditionally modify Rn with the + result of the comparison, within the delay slot of + the branch. This is used by older gcc. */ + NEXT_INSN; + if ((ctx->opcode & 0xf0ff) =3D=3D 0x0029) { /* movt Rn */ + mt_reg =3D B11_8; + } else { + goto fail; + } + break; + + default: + goto fail; + } + break; + + default: + /* Put back and re-examine as store. */ + --i; + } + + /* + * Expect the store. + */ + /* The store must be the last insn. */ + if (i !=3D max_insns - 1) { + goto fail; + } + NEXT_INSN; + switch (ctx->opcode & 0xf00f) { + case 0x2000: /* mov.b Rm,@Rn */ + st_mop =3D MO_UB; + break; + case 0x2001: /* mov.w Rm,@Rn */ + st_mop =3D MO_UW; + break; + case 0x2002: /* mov.l Rm,@Rn */ + st_mop =3D MO_UL; + break; + default: + goto fail; + } + /* The store must match the load. */ + if (ld_adr !=3D B11_8 || st_mop !=3D (ld_mop & MO_SIZE)) { + goto fail; + } + st_reg =3D B7_4; + +#undef NEXT_INSN + + /* + * Emit the operation. + */ + tcg_gen_insn_start(pc, ctx->envflags); + switch (op_opc) { + case -1: + /* No operation found. Look for exchange pattern. */ + if (st_reg =3D=3D ld_reg || st_reg =3D=3D op_reg) { + goto fail; + } + tcg_gen_atomic_xchg_i32(REG(ld_reg), REG(ld_adr), REG(st_reg), + ctx->memidx, ld_mop); + break; + + case INDEX_op_add_i32: + if (op_reg !=3D st_reg) { + goto fail; + } + if (op_reg =3D=3D ld_reg && st_mop =3D=3D MO_UL) { + tcg_gen_atomic_add_fetch_i32(REG(ld_reg), REG(ld_adr), + REG(op_arg), ctx->memidx, ld_mop); + } else { + tcg_gen_atomic_fetch_add_i32(REG(ld_reg), REG(ld_adr), + REG(op_arg), ctx->memidx, ld_mop); + if (op_reg !=3D ld_reg) { + /* Note that mop sizes < 4 cannot use add_fetch + because it won't carry into the higher bits. */ + tcg_gen_add_i32(REG(op_reg), REG(ld_reg), REG(op_arg)); + } + } + break; + + case INDEX_op_and_i32: + if (op_reg !=3D st_reg) { + goto fail; + } + if (op_reg =3D=3D ld_reg) { + tcg_gen_atomic_and_fetch_i32(REG(ld_reg), REG(ld_adr), + REG(op_arg), ctx->memidx, ld_mop); + } else { + tcg_gen_atomic_fetch_and_i32(REG(ld_reg), REG(ld_adr), + REG(op_arg), ctx->memidx, ld_mop); + tcg_gen_and_i32(REG(op_reg), REG(ld_reg), REG(op_arg)); + } + break; + + case INDEX_op_or_i32: + if (op_reg !=3D st_reg) { + goto fail; + } + if (op_reg =3D=3D ld_reg) { + tcg_gen_atomic_or_fetch_i32(REG(ld_reg), REG(ld_adr), + REG(op_arg), ctx->memidx, ld_mop); + } else { + tcg_gen_atomic_fetch_or_i32(REG(ld_reg), REG(ld_adr), + REG(op_arg), ctx->memidx, ld_mop); + tcg_gen_or_i32(REG(op_reg), REG(ld_reg), REG(op_arg)); + } + break; + + case INDEX_op_xor_i32: + if (op_reg !=3D st_reg) { + goto fail; + } + if (op_reg =3D=3D ld_reg) { + tcg_gen_atomic_xor_fetch_i32(REG(ld_reg), REG(ld_adr), + REG(op_arg), ctx->memidx, ld_mop); + } else { + tcg_gen_atomic_fetch_xor_i32(REG(ld_reg), REG(ld_adr), + REG(op_arg), ctx->memidx, ld_mop); + tcg_gen_xor_i32(REG(op_reg), REG(ld_reg), REG(op_arg)); + } + break; =20 + case INDEX_op_setcond_i32: + if (st_reg =3D=3D ld_reg) { + goto fail; + } + tcg_gen_atomic_cmpxchg_i32(REG(ld_reg), REG(ld_adr), REG(op_arg), + REG(st_reg), ctx->memidx, ld_mop); + tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_t, REG(ld_reg), REG(op_arg= )); + if (mt_reg >=3D 0) { + tcg_gen_mov_i32(REG(mt_reg), cpu_sr_t); + } + break; + + default: + g_assert_not_reached(); + } + + /* The entire region has been translated. */ + ctx->envflags &=3D ~GUSA_MASK; + ctx->pc =3D pc_end; + return max_insns; + + fail: qemu_log_mask(LOG_UNIMP, "Unrecognized gUSA sequence %08x-%08x\n", pc, pc_end); =20 @@ -1913,8 +2198,8 @@ static int decode_gusa(DisasContext *ctx) ctx->bstate =3D BS_EXCP; =20 /* We're not executing an instruction, but we must report one for the - purposes of accounting within the TB. At which point we might as - well report the entire region so that it's immediately available + purposes of accounting within the TB. We might as well report the + entire region consumed via ctx->pc so that it's immediately availab= le in the disassembly dump. */ ctx->pc =3D pc_end; return 1; @@ -1966,13 +2251,8 @@ void gen_intermediate_code(CPUSH4State * env, struct= TranslationBlock *tb) num_insns =3D 0; =20 #ifdef CONFIG_USER_ONLY - if (ctx.tbflags & GUSA_EXCLUSIVE) { - /* Regardless of single-stepping or the end of the page, - we must complete execution of the gUSA region while - holding the exclusive lock. */ - max_insns =3D (tb->cs_base - ctx.pc) / 2; - } else if (ctx.tbflags & GUSA_MASK) { - num_insns =3D decode_gusa(&ctx); + if (ctx.tbflags & GUSA_MASK) { + num_insns =3D decode_gusa(&ctx, env, &max_insns); } #endif =20 --=20 2.9.4 From nobody Wed Nov 5 08:02:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499301164013319.28892606806835; Wed, 5 Jul 2017 17:32:44 -0700 (PDT) Received: from localhost ([::1]:48666 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSuio-0006F2-PO for importer@patchew.org; Wed, 05 Jul 2017 20:32:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59715) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSub0-0007X1-UF for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSub0-0002QD-1j for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:38 -0400 Received: from mail-qk0-x242.google.com ([2607:f8b0:400d:c09::242]:35763) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dSuaz-0002Q9-UJ for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:37 -0400 Received: by mail-qk0-x242.google.com with SMTP id 16so647437qkg.2 for ; Wed, 05 Jul 2017 17:24:37 -0700 (PDT) Received: from bigtime.twiddle.net.com (rrcs-66-91-136-156.west.biz.rr.com. [66.91.136.156]) by smtp.gmail.com with ESMTPSA id u85sm371825qku.42.2017.07.05.17.24.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Jul 2017 17:24:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=s+oYQy25aXT5Zzsl2mzTcm8EwPd5P/rkdD6RntgzB8I=; b=ng7JNASdj//vlISQwAW/dSmJGlliKC98GfS3F0r0HnYtmMuthw+TDB9210HILU+Rm/ cPWPb6Vv5TAO5IbgW3pn5SXK1eAKcQv5JF+qHN81BwsXGbaR317jS1gTPKgpNEXadi3H XsaBrBO/K5Gh+P24lP59aZ45NxlgKOw+K9285VFeImpTP1EvOfAtAStbJXTNHtyTu8Ra +TtWXss8A4Z3bsQDQqvDbZJRskyVoJQ0Mxwcmj2S27tf/lJjAOd4ZopCtTJXZDiHzfuW pAN1Sb5x540twxYcpO+KB0T2Q5JS5CdayunSSgTVanktgvQPDxKHXsS0B6uvDCMXTzPr lBiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=s+oYQy25aXT5Zzsl2mzTcm8EwPd5P/rkdD6RntgzB8I=; b=M1ppYpfvytTFUt1Dt0N1+cpDJ3Za3hnVGIqmqR14U4XY4WVYVtpkdURl1OYuX1UHg/ RwSKV3CYyv6djarWH2D4yMU5GjTf9Mg3ucImz4WO/TaVN5tgCd/KNZhyvyigQj+xr+zu PLz9aMyiJhuKmOVJfKwoWDy4JH4w+sIpEjPGqKC8MuiliXB4D4Ynr1gLy4m77JeO+D7D v1zDjvXm6wTC1N+qHkJBXqPdqVtcPQMORnCVRdWeeyx7XEIXs+pPQvnHetUP6d1WWN2w 8lKTCeKXAeLYHaky4Sq+4qvgW3Ctl/N0x2GantxwgKdhm8BW5DmMzKqE+uG/A4lBBTst WikA== X-Gm-Message-State: AIVw110Ipuylj89XczeqDhNQiNEQp+kSYVy4++kYWoVegv0NrRogPDUt SD4F33lVaIgmyFT2kCY= X-Received: by 10.55.21.135 with SMTP id 7mr10117888qkv.52.1499300677167; Wed, 05 Jul 2017 17:24:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 5 Jul 2017 14:23:55 -1000 Message-Id: <20170706002401.10507-6-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170706002401.10507-1-rth@twiddle.net> References: <20170706002401.10507-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::242 Subject: [Qemu-devel] [PATCH 05/11] linux-user/sh4: Notice gUSA regions during signal delivery X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno@clisp.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We translate gUSA regions atomically in a parallel context. But in a serial context a gUSA region may be interrupted. In that case, restart the region as the kernel would. Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier --- linux-user/signal.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/linux-user/signal.c b/linux-user/signal.c index 3d18d1b..1e716a9 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -3471,6 +3471,23 @@ static abi_ulong get_sigframe(struct target_sigactio= n *ka, return (sp - frame_size) & -8ul; } =20 +/* Notice when we're in the middle of a gUSA region and reset. + Note that this will only occur for !parallel_cpus, as we will + translate such sequences differently in a parallel context. */ +static void unwind_gusa(CPUSH4State *regs) +{ + /* If the stack pointer is sufficiently negative... */ + if ((regs->gregs[15] & 0xc0000000u) =3D=3D 0xc0000000u) { + /* Reset the PC to before the gUSA region, as computed from + R0 =3D region end, SP =3D -(region size), plus one more insn + that actually sets SP to the region size. */ + regs->pc =3D regs->gregs[0] + regs->gregs[15] - 2; + + /* Reset the SP to the saved version in R1. */ + regs->gregs[15] =3D regs->gregs[1]; + } +} + static void setup_sigcontext(struct target_sigcontext *sc, CPUSH4State *regs, unsigned long mask) { @@ -3534,6 +3551,8 @@ static void setup_frame(int sig, struct target_sigact= ion *ka, abi_ulong frame_addr; int i; =20 + unwind_gusa(regs); + frame_addr =3D get_sigframe(ka, regs->gregs[15], sizeof(*frame)); trace_user_setup_frame(regs, frame_addr); if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) { @@ -3583,6 +3602,8 @@ static void setup_rt_frame(int sig, struct target_sig= action *ka, abi_ulong frame_addr; int i; =20 + unwind_gusa(regs); + frame_addr =3D get_sigframe(ka, regs->gregs[15], sizeof(*frame)); trace_user_setup_rt_frame(regs, frame_addr); if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) { --=20 2.9.4 From nobody Wed Nov 5 08:02:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499300924317634.1483836339683; Wed, 5 Jul 2017 17:28:44 -0700 (PDT) Received: from localhost ([::1]:48643 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSuex-0002BX-4D for importer@patchew.org; Wed, 05 Jul 2017 20:28:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59729) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSub6-0007aP-CX for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSub3-0002R0-7S for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:44 -0400 Received: from mail-qk0-x244.google.com ([2607:f8b0:400d:c09::244]:33022) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dSub3-0002Qs-3B for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:41 -0400 Received: by mail-qk0-x244.google.com with SMTP id p21so661623qke.0 for ; Wed, 05 Jul 2017 17:24:41 -0700 (PDT) Received: from bigtime.twiddle.net.com (rrcs-66-91-136-156.west.biz.rr.com. [66.91.136.156]) by smtp.gmail.com with ESMTPSA id u85sm371825qku.42.2017.07.05.17.24.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Jul 2017 17:24:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=Zp8YYJ2hiucuGOTk/wf7u4b8kU479haBP6qTewRFrjM=; b=t3JlwPR4cK/xtaCe+QEwO18O2CrEEDgrV2Chw7nytZeOgxeBN88K6qMa62suHv01gw QQD2VBKUc0NUUo0qG7pr+myHFaSy0ipixVyW12jkVNavQ6kQwxIxIjlQNpvOKq4Gi2Bl xlv2qmr0/1pnYe8Rdq0fzBP1WLzMgZUm0qOwh4duglNqojrmKVg87uafIKq0mnUeW2wj P+XRbGIsMbCpnxXq63LXfX7pAGUcw7flQfKWp9trGdc1hM4gnVcnPux6FUFy4bYSbHSI AvWVSFEdxtqNDCxNK8/0ISHQR9WTRX+lCI8UGOmizbAmeaePGBo9v8rs//ExX69/oku0 gHdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=Zp8YYJ2hiucuGOTk/wf7u4b8kU479haBP6qTewRFrjM=; b=P5tiu1VsnXqQdnCDAMnaqJSDm9cMsjE5x8Ojvw10ScWuJQm6G1Snh+fakko/wggAJS 9yJQ0e8v0/w3XmiwP0BlpmdI8rJvCNRLtVK7ahcPWKkGCqgcty33e8vLrJ2RVe73X4Lv tyMbxgVoK2zwhVIqDmWeYDxDGWV4D0LgAjLiHaigbXoHGXK8eASQr5DqDGcLfo3TZa6f TDs5oyhDoveFJ2nzkgudngY5D+QmciraOcJV+14YWJx0DhWW+xDt3wQXAlBjizBE7uEA F9mmbzWpYwqWn+szT7qPKAZ+810jQgW/uGMpzEpK4PAZo/iePSCRKtT07NKNL4oAtcoN gnug== X-Gm-Message-State: AKS2vOz6Ap8GmeXVot74+rAtQuRr//j1Un5AHx+qz/z09lmxHP8wN/el kpIMrmPcabm195DvjZE= X-Received: by 10.55.181.71 with SMTP id e68mr54912742qkf.91.1499300680312; Wed, 05 Jul 2017 17:24:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 5 Jul 2017 14:23:56 -1000 Message-Id: <20170706002401.10507-7-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170706002401.10507-1-rth@twiddle.net> References: <20170706002401.10507-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-devel] [PATCH 06/11] target/sh4: Hoist register bank selection X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno@clisp.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Compute which register bank to use once at the start of translation. Signed-off-by: Richard Henderson --- target/sh4/translate.c | 43 ++++++++++++++++++++++++++++++------------- 1 file changed, 30 insertions(+), 13 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 9ab7d6e..20e24d5 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -35,6 +35,8 @@ =20 typedef struct DisasContext { struct TranslationBlock *tb; + TCGv *gregs; /* active bank */ + TCGv *altregs; /* inactive, alternate, bank */ target_ulong pc; uint16_t opcode; uint32_t tbflags; /* should stay unmodified during the TB translati= on */ @@ -64,7 +66,7 @@ enum { =20 /* global register indexes */ static TCGv_env cpu_env; -static TCGv cpu_gregs[24]; +static TCGv cpu_gregs[2][16]; static TCGv cpu_sr, cpu_sr_m, cpu_sr_q, cpu_sr_t; static TCGv cpu_pc, cpu_ssr, cpu_spc, cpu_gbr; static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl; @@ -99,16 +101,31 @@ void sh4_translate_init(void) "FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1", }; =20 - if (done_init) + if (done_init) { return; + } =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); tcg_ctx.tcg_env =3D cpu_env; =20 - for (i =3D 0; i < 24; i++) - cpu_gregs[i] =3D tcg_global_mem_new_i32(cpu_env, - offsetof(CPUSH4State, gregs[= i]), - gregnames[i]); + for (i =3D 0; i < 8; i++) { + cpu_gregs[0][i] + =3D tcg_global_mem_new_i32(cpu_env, + offsetof(CPUSH4State, gregs[i]), + gregnames[i]); + } + for (i =3D 8; i < 16; i++) { + cpu_gregs[0][i] =3D cpu_gregs[1][i] + =3D tcg_global_mem_new_i32(cpu_env, + offsetof(CPUSH4State, gregs[i]), + gregnames[i]); + } + for (i =3D 16; i < 24; i++) { + cpu_gregs[1][i - 16] + =3D tcg_global_mem_new_i32(cpu_env, + offsetof(CPUSH4State, gregs[i]), + gregnames[i]); + } =20 cpu_pc =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUSH4State, pc), "PC"); @@ -362,13 +379,8 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int re= g) #define B11_8 ((ctx->opcode >> 8) & 0xf) #define B15_12 ((ctx->opcode >> 12) & 0xf) =20 -#define REG(x) ((x) < 8 && (ctx->tbflags & (1u << SR_MD))\ - && (ctx->tbflags & (1u << SR_RB))\ - ? (cpu_gregs[x + 16]) : (cpu_gregs[x])) - -#define ALTREG(x) ((x) < 8 && (!(ctx->tbflags & (1u << SR_MD))\ - || !(ctx->tbflags & (1u << SR_RB)))\ - ? (cpu_gregs[x + 16]) : (cpu_gregs[x])) +#define REG(x) ctx->gregs[x] +#define ALTREG(x) ctx->altregs[x] =20 #define FREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)) #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) @@ -2214,6 +2226,7 @@ void gen_intermediate_code(CPUSH4State * env, struct = TranslationBlock *tb) target_ulong pc_start; int num_insns; int max_insns; + int bank; =20 pc_start =3D tb->pc; ctx.pc =3D pc_start; @@ -2229,6 +2242,10 @@ void gen_intermediate_code(CPUSH4State * env, struct= TranslationBlock *tb) ctx.features =3D env->features; ctx.has_movcal =3D (ctx.tbflags & TB_FLAG_PENDING_MOVCA); =20 + bank =3D (ctx.tbflags & (1 << SR_MD)) && (ctx.tbflags & (1 << SR_RB)); + ctx.gregs =3D cpu_gregs[bank]; + ctx.altregs =3D cpu_gregs[bank ^ 1]; + max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; --=20 2.9.4 From nobody Wed Nov 5 08:02:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499300945765882.8151476984954; Wed, 5 Jul 2017 17:29:05 -0700 (PDT) Received: from localhost ([::1]:48644 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSufI-00034h-F4 for importer@patchew.org; Wed, 05 Jul 2017 20:29:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59739) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSub7-0007aR-GX for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSub5-0002RV-SS for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:45 -0400 Received: from mail-qt0-x244.google.com ([2607:f8b0:400d:c0d::244]:32809) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dSub5-0002RR-Na for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:43 -0400 Received: by mail-qt0-x244.google.com with SMTP id c20so651159qte.0 for ; Wed, 05 Jul 2017 17:24:43 -0700 (PDT) Received: from bigtime.twiddle.net.com (rrcs-66-91-136-156.west.biz.rr.com. [66.91.136.156]) by smtp.gmail.com with ESMTPSA id u85sm371825qku.42.2017.07.05.17.24.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Jul 2017 17:24:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=L81op+57OmzC4fnmOGL4RaFTHM8RMh0bUgEIZBEdZvU=; b=spjiW2Ws+bhJEh7UVJyv36YBFG7MTHpbjDC7z/DkitS0PlFBgTl4BKFLZogXaDtFIr 3FYvT43Noava8sO5aprQmX3hp/oYVrWwEiL1zX56hidGQxLGDCvc4w2ISGKx9w9vcE7E G61x7LPh+vS3p/Nwb6nDAa3Q79AQ9xN3pUE+WAlO+fY6VRDDnTQ1YNmGgGZZe8PgNgvK hZ14CL07jdb554/wmv3r7bQTXcVXyZgobSMqwPwE1t4MENAK/2rRDv0HmBdUO4sb072M 35RIfZzQYhj/muORnT+5DcU69x+FakaW3i3VlfWHejnBCo6/v9sVz3j/MEH+FE3pR2U4 qiZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=L81op+57OmzC4fnmOGL4RaFTHM8RMh0bUgEIZBEdZvU=; b=f3EeKFDrpW0axrbOQQ8IGh1R9QP8dCkHhWqOy09NsKuxahMAa9RNkBzicRuTNC1mkZ gCXzzD6rYL96f+bIiIqrMYU3BItLW0FSEe8hwM85mLodRUQWe/LZEZamuSr/z9dVoiye OSibWC0oKdVQZPIin9UOkKpSulIQ1h95BbZDd3RD3AKy36VShlddKDHHdxnjPUHZ8Hha TSz3lcKuD9XGOxHuTheGyT84lBYgt5lVFg0QXpnGTy57eAabsOIK61nbkzZgXXVhntWi gEpWMU749sSLpF7d4nbzy1LyLHXgEfsmL7bQPW3mj+OxQsRSvxTx/9YsxchAwEdbIOX6 Bx3g== X-Gm-Message-State: AIVw110E2TXftAiIRm0BT1iGazFEQqRJE84LUiHDgSN7mFseW/FEe5Bb lCIMrjBwq4B/uWsCTzo= X-Received: by 10.237.32.196 with SMTP id 62mr16557766qtb.99.1499300682996; Wed, 05 Jul 2017 17:24:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 5 Jul 2017 14:23:57 -1000 Message-Id: <20170706002401.10507-8-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170706002401.10507-1-rth@twiddle.net> References: <20170706002401.10507-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::244 Subject: [Qemu-devel] [PATCH 07/11] target/sh4: Unify cpu_fregs into FREG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno@clisp.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We were treating FREG as an index and REG as a TCGv. Making FREG return a TCGv is both less confusing and a step toward cleaner banking of cpu_fregs. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/sh4/translate.c | 123 +++++++++++++++++++++------------------------= ---- 1 file changed, 52 insertions(+), 71 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 20e24d5..e4fd6f2 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -382,10 +382,11 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int r= eg) #define REG(x) ctx->gregs[x] #define ALTREG(x) ctx->altregs[x] =20 -#define FREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)) +#define FREG(x) cpu_fregs[ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)] #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) -#define XREG(x) (ctx->tbflags & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x)) -#define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */ +#define XREG(x) FREG(XHACK(x)) +/* Assumes lsb of (x) is always 0 */ +#define DREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)) =20 #define CHECK_NOT_DELAY_SLOT \ if (ctx->envflags & DELAY_SLOT_MASK) { \ @@ -1005,56 +1006,51 @@ static void _decode_opc(DisasContext * ctx) CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { TCGv_i64 fp =3D tcg_temp_new_i64(); - gen_load_fpr64(fp, XREG(B7_4)); - gen_store_fpr64(fp, XREG(B11_8)); + gen_load_fpr64(fp, XHACK(B7_4)); + gen_store_fpr64(fp, XHACK(B11_8)); tcg_temp_free_i64(fp); } else { - tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); + tcg_gen_mov_i32(FREG(B11_8), FREG(B7_4)); } return; case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { TCGv addr_hi =3D tcg_temp_new(); - int fr =3D XREG(B7_4); + int fr =3D XHACK(B7_4); tcg_gen_addi_i32(addr_hi, REG(B11_8), 4); - tcg_gen_qemu_st_i32(cpu_fregs[fr], REG(B11_8), - ctx->memidx, MO_TEUL); - tcg_gen_qemu_st_i32(cpu_fregs[fr+1], addr_hi, - ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(FREG(fr), REG(B11_8), ctx->memidx, MO_TEUL= ); + tcg_gen_qemu_st_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEU= L); tcg_temp_free(addr_hi); } else { - tcg_gen_qemu_st_i32(cpu_fregs[FREG(B7_4)], REG(B11_8), - ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(FREG(B7_4), REG(B11_8), ctx->memidx, MO_TE= UL); } return; case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { TCGv addr_hi =3D tcg_temp_new(); - int fr =3D XREG(B11_8); + int fr =3D XHACK(B11_8); tcg_gen_addi_i32(addr_hi, REG(B7_4), 4); - tcg_gen_qemu_ld_i32(cpu_fregs[fr], REG(B7_4), ctx->memidx, MO_= TEUL); - tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr_hi, ctx->memidx, MO_= TEUL); + tcg_gen_qemu_ld_i32(FREG(fr), REG(B7_4), ctx->memidx, MO_TEUL); + tcg_gen_qemu_ld_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEU= L); tcg_temp_free(addr_hi); } else { - tcg_gen_qemu_ld_i32(cpu_fregs[FREG(B11_8)], REG(B7_4), - ctx->memidx, MO_TEUL); + tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TE= UL); } return; case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { TCGv addr_hi =3D tcg_temp_new(); - int fr =3D XREG(B11_8); + int fr =3D XHACK(B11_8); tcg_gen_addi_i32(addr_hi, REG(B7_4), 4); - tcg_gen_qemu_ld_i32(cpu_fregs[fr], REG(B7_4), ctx->memidx, MO_= TEUL); - tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr_hi, ctx->memidx, MO_= TEUL); + tcg_gen_qemu_ld_i32(FREG(fr), REG(B7_4), ctx->memidx, MO_TEUL); + tcg_gen_qemu_ld_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEU= L); tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8); tcg_temp_free(addr_hi); } else { - tcg_gen_qemu_ld_i32(cpu_fregs[FREG(B11_8)], REG(B7_4), - ctx->memidx, MO_TEUL); + tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TE= UL); tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); } return; @@ -1063,13 +1059,12 @@ static void _decode_opc(DisasContext * ctx) TCGv addr =3D tcg_temp_new_i32(); tcg_gen_subi_i32(addr, REG(B11_8), 4); if (ctx->tbflags & FPSCR_SZ) { - int fr =3D XREG(B7_4); - tcg_gen_qemu_st_i32(cpu_fregs[fr+1], addr, ctx->memidx, MO_TEU= L); + int fr =3D XHACK(B7_4); + tcg_gen_qemu_st_i32(FREG(fr + 1), addr, ctx->memidx, MO_TEUL); tcg_gen_subi_i32(addr, addr, 4); - tcg_gen_qemu_st_i32(cpu_fregs[fr], addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(FREG(fr), addr, ctx->memidx, MO_TEUL); } else { - tcg_gen_qemu_st_i32(cpu_fregs[FREG(B7_4)], addr, - ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL); } tcg_gen_mov_i32(REG(B11_8), addr); tcg_temp_free(addr); @@ -1080,15 +1075,12 @@ static void _decode_opc(DisasContext * ctx) TCGv addr =3D tcg_temp_new_i32(); tcg_gen_add_i32(addr, REG(B7_4), REG(0)); if (ctx->tbflags & FPSCR_SZ) { - int fr =3D XREG(B11_8); - tcg_gen_qemu_ld_i32(cpu_fregs[fr], addr, - ctx->memidx, MO_TEUL); + int fr =3D XHACK(B11_8); + tcg_gen_qemu_ld_i32(FREG(fr), addr, ctx->memidx, MO_TEUL); tcg_gen_addi_i32(addr, addr, 4); - tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr, - ctx->memidx, MO_TEUL); + tcg_gen_qemu_ld_i32(FREG(fr + 1), addr, ctx->memidx, MO_TE= UL); } else { - tcg_gen_qemu_ld_i32(cpu_fregs[FREG(B11_8)], addr, - ctx->memidx, MO_TEUL); + tcg_gen_qemu_ld_i32(FREG(B11_8), addr, ctx->memidx, MO_TEU= L); } tcg_temp_free(addr); } @@ -1099,15 +1091,12 @@ static void _decode_opc(DisasContext * ctx) TCGv addr =3D tcg_temp_new(); tcg_gen_add_i32(addr, REG(B11_8), REG(0)); if (ctx->tbflags & FPSCR_SZ) { - int fr =3D XREG(B7_4); - tcg_gen_qemu_ld_i32(cpu_fregs[fr], addr, - ctx->memidx, MO_TEUL); + int fr =3D XHACK(B7_4); + tcg_gen_qemu_ld_i32(FREG(fr), addr, ctx->memidx, MO_TEUL); tcg_gen_addi_i32(addr, addr, 4); - tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr, - ctx->memidx, MO_TEUL); + tcg_gen_qemu_ld_i32(FREG(fr + 1), addr, ctx->memidx, MO_TE= UL); } else { - tcg_gen_qemu_st_i32(cpu_fregs[FREG(B7_4)], addr, - ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL= ); } tcg_temp_free(addr); } @@ -1155,32 +1144,26 @@ static void _decode_opc(DisasContext * ctx) } else { switch (ctx->opcode & 0xf00f) { case 0xf000: /* fadd Rm,Rn */ - gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_env, - cpu_fregs[FREG(B11_8)], - cpu_fregs[FREG(B7_4)]); + gen_helper_fadd_FT(FREG(B11_8), cpu_env, + FREG(B11_8), FREG(B7_4)); break; case 0xf001: /* fsub Rm,Rn */ - gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_env, - cpu_fregs[FREG(B11_8)], - cpu_fregs[FREG(B7_4)]); + gen_helper_fsub_FT(FREG(B11_8), cpu_env, + FREG(B11_8), FREG(B7_4)); break; case 0xf002: /* fmul Rm,Rn */ - gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_env, - cpu_fregs[FREG(B11_8)], - cpu_fregs[FREG(B7_4)]); + gen_helper_fmul_FT(FREG(B11_8), cpu_env, + FREG(B11_8), FREG(B7_4)); break; case 0xf003: /* fdiv Rm,Rn */ - gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_env, - cpu_fregs[FREG(B11_8)], - cpu_fregs[FREG(B7_4)]); + gen_helper_fdiv_FT(FREG(B11_8), cpu_env, + FREG(B11_8), FREG(B7_4)); break; case 0xf004: /* fcmp/eq Rm,Rn */ - gen_helper_fcmp_eq_FT(cpu_env, cpu_fregs[FREG(B11_8)], - cpu_fregs[FREG(B7_4)]); + gen_helper_fcmp_eq_FT(cpu_env, FREG(B11_8), FREG(B7_4)= ); return; case 0xf005: /* fcmp/gt Rm,Rn */ - gen_helper_fcmp_gt_FT(cpu_env, cpu_fregs[FREG(B11_8)], - cpu_fregs[FREG(B7_4)]); + gen_helper_fcmp_gt_FT(cpu_env, FREG(B11_8), FREG(B7_4)= ); return; } } @@ -1192,9 +1175,8 @@ static void _decode_opc(DisasContext * ctx) if (ctx->tbflags & FPSCR_PR) { break; /* illegal instruction */ } else { - gen_helper_fmac_FT(cpu_fregs[FREG(B11_8)], cpu_env, - cpu_fregs[FREG(0)], cpu_fregs[FREG(B7_4= )], - cpu_fregs[FREG(B11_8)]); + gen_helper_fmac_FT(FREG(B11_8), cpu_env, + FREG(0), FREG(B7_4), FREG(B11_8)); return; } } @@ -1732,11 +1714,11 @@ static void _decode_opc(DisasContext * ctx) return; case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ CHECK_FPU_ENABLED - tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fpul); + tcg_gen_mov_i32(FREG(B11_8), cpu_fpul); return; case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */ CHECK_FPU_ENABLED - tcg_gen_mov_i32(cpu_fpul, cpu_fregs[FREG(B11_8)]); + tcg_gen_mov_i32(cpu_fpul, FREG(B11_8)); return; case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Fla= g] */ CHECK_FPU_ENABLED @@ -1750,7 +1732,7 @@ static void _decode_opc(DisasContext * ctx) tcg_temp_free_i64(fp); } else { - gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_env, cpu_fpul); + gen_helper_float_FT(FREG(B11_8), cpu_env, cpu_fpul); } return; case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag= ] */ @@ -1765,13 +1747,13 @@ static void _decode_opc(DisasContext * ctx) tcg_temp_free_i64(fp); } else { - gen_helper_ftrc_FT(cpu_fpul, cpu_env, cpu_fregs[FREG(B11_8)]); + gen_helper_ftrc_FT(cpu_fpul, cpu_env, FREG(B11_8)); } return; case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ CHECK_FPU_ENABLED { - gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); + gen_helper_fneg_T(FREG(B11_8), FREG(B11_8)); } return; case 0xf05d: /* fabs FRn/DRn */ @@ -1785,7 +1767,7 @@ static void _decode_opc(DisasContext * ctx) gen_store_fpr64(fp, DREG(B11_8)); tcg_temp_free_i64(fp); } else { - gen_helper_fabs_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); + gen_helper_fabs_FT(FREG(B11_8), FREG(B11_8)); } return; case 0xf06d: /* fsqrt FRn */ @@ -1799,8 +1781,7 @@ static void _decode_opc(DisasContext * ctx) gen_store_fpr64(fp, DREG(B11_8)); tcg_temp_free_i64(fp); } else { - gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_env, - cpu_fregs[FREG(B11_8)]); + gen_helper_fsqrt_FT(FREG(B11_8), cpu_env, FREG(B11_8)); } return; case 0xf07d: /* fsrra FRn */ @@ -1809,13 +1790,13 @@ static void _decode_opc(DisasContext * ctx) case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ CHECK_FPU_ENABLED if (!(ctx->tbflags & FPSCR_PR)) { - tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0); + tcg_gen_movi_i32(FREG(B11_8), 0); } return; case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ CHECK_FPU_ENABLED if (!(ctx->tbflags & FPSCR_PR)) { - tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000); + tcg_gen_movi_i32(FREG(B11_8), 0x3f800000); } return; case 0xf0ad: /* fcnvsd FPUL,DRn */ --=20 2.9.4 From nobody Wed Nov 5 08:02:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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X-Received-From: 2607:f8b0:400d:c0d::243 Subject: [Qemu-devel] [PATCH 08/11] target/sh4: Pass DisasContext to fpr64 routines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno@clisp.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/sh4/translate.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index e4fd6f2..05657a9 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -359,12 +359,12 @@ static void gen_delayed_conditional_jump(DisasContext= * ctx) gen_jump(ctx); } =20 -static inline void gen_load_fpr64(TCGv_i64 t, int reg) +static inline void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]); } =20 -static inline void gen_store_fpr64 (TCGv_i64 t, int reg) +static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { tcg_gen_extr_i64_i32(cpu_fregs[reg + 1], cpu_fregs[reg], t); } @@ -1006,8 +1006,8 @@ static void _decode_opc(DisasContext * ctx) CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { TCGv_i64 fp =3D tcg_temp_new_i64(); - gen_load_fpr64(fp, XHACK(B7_4)); - gen_store_fpr64(fp, XHACK(B11_8)); + gen_load_fpr64(ctx, fp, XHACK(B7_4)); + gen_store_fpr64(ctx, fp, XHACK(B11_8)); tcg_temp_free_i64(fp); } else { tcg_gen_mov_i32(FREG(B11_8), FREG(B7_4)); @@ -1116,8 +1116,8 @@ static void _decode_opc(DisasContext * ctx) break; /* illegal instruction */ fp0 =3D tcg_temp_new_i64(); fp1 =3D tcg_temp_new_i64(); - gen_load_fpr64(fp0, DREG(B11_8)); - gen_load_fpr64(fp1, DREG(B7_4)); + gen_load_fpr64(ctx, fp0, DREG(B11_8)); + gen_load_fpr64(ctx, fp1, DREG(B7_4)); switch (ctx->opcode & 0xf00f) { case 0xf000: /* fadd Rm,Rn */ gen_helper_fadd_DT(fp0, cpu_env, fp0, fp1); @@ -1138,7 +1138,7 @@ static void _decode_opc(DisasContext * ctx) gen_helper_fcmp_gt_DT(cpu_env, fp0, fp1); return; } - gen_store_fpr64(fp0, DREG(B11_8)); + gen_store_fpr64(ctx, fp0, DREG(B11_8)); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); } else { @@ -1728,7 +1728,7 @@ static void _decode_opc(DisasContext * ctx) break; /* illegal instruction */ fp =3D tcg_temp_new_i64(); gen_helper_float_DT(fp, cpu_env, cpu_fpul); - gen_store_fpr64(fp, DREG(B11_8)); + gen_store_fpr64(ctx, fp, DREG(B11_8)); tcg_temp_free_i64(fp); } else { @@ -1742,7 +1742,7 @@ static void _decode_opc(DisasContext * ctx) if (ctx->opcode & 0x0100) break; /* illegal instruction */ fp =3D tcg_temp_new_i64(); - gen_load_fpr64(fp, DREG(B11_8)); + gen_load_fpr64(ctx, fp, DREG(B11_8)); gen_helper_ftrc_DT(cpu_fpul, cpu_env, fp); tcg_temp_free_i64(fp); } @@ -1762,9 +1762,9 @@ static void _decode_opc(DisasContext * ctx) if (ctx->opcode & 0x0100) break; /* illegal instruction */ TCGv_i64 fp =3D tcg_temp_new_i64(); - gen_load_fpr64(fp, DREG(B11_8)); + gen_load_fpr64(ctx, fp, DREG(B11_8)); gen_helper_fabs_DT(fp, fp); - gen_store_fpr64(fp, DREG(B11_8)); + gen_store_fpr64(ctx, fp, DREG(B11_8)); tcg_temp_free_i64(fp); } else { gen_helper_fabs_FT(FREG(B11_8), FREG(B11_8)); @@ -1776,9 +1776,9 @@ static void _decode_opc(DisasContext * ctx) if (ctx->opcode & 0x0100) break; /* illegal instruction */ TCGv_i64 fp =3D tcg_temp_new_i64(); - gen_load_fpr64(fp, DREG(B11_8)); + gen_load_fpr64(ctx, fp, DREG(B11_8)); gen_helper_fsqrt_DT(fp, cpu_env, fp); - gen_store_fpr64(fp, DREG(B11_8)); + gen_store_fpr64(ctx, fp, DREG(B11_8)); tcg_temp_free_i64(fp); } else { gen_helper_fsqrt_FT(FREG(B11_8), cpu_env, FREG(B11_8)); @@ -1804,7 +1804,7 @@ static void _decode_opc(DisasContext * ctx) { TCGv_i64 fp =3D tcg_temp_new_i64(); gen_helper_fcnvsd_FT_DT(fp, cpu_env, cpu_fpul); - gen_store_fpr64(fp, DREG(B11_8)); + gen_store_fpr64(ctx, fp, DREG(B11_8)); tcg_temp_free_i64(fp); } return; @@ -1812,7 +1812,7 @@ static void _decode_opc(DisasContext * ctx) CHECK_FPU_ENABLED { TCGv_i64 fp =3D tcg_temp_new_i64(); - gen_load_fpr64(fp, DREG(B11_8)); + gen_load_fpr64(ctx, fp, DREG(B11_8)); gen_helper_fcnvds_DT_FT(cpu_fpul, cpu_env, fp); tcg_temp_free_i64(fp); } --=20 2.9.4 From nobody Wed Nov 5 08:02:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499301132312406.6175394033735; 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[66.91.136.156]) by smtp.gmail.com with ESMTPSA id u85sm371825qku.42.2017.07.05.17.24.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Jul 2017 17:24:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZLrv7XiB31CYgQy686NY+c/cajh5RqkEfQmHjWEpDZo=; b=Kdt9hxnWqSnqYubmnMrfD1RiXUs9h5Jwx838ucW4DJ+Z96P8A1iXgTSsDmh8Co+pjO ZihBeU/pa77TaI+SM4bkjzMfBpWAC1cclwU1TZVrSU+SwbkSVuZECv9nOCpZb/ShbGto 3wDfVCjhLXlakT1MsG43dEWUBzXDSSlxMKdrn96s4BTNnl6Z+dH6usvIG4hzTe8ba19t j5RTDFxOIWYWM0FOsNT/kQm5LyVGvfTHySnoCanEX0d0Ix+foMkpzTCjHB6XETS2XdrB zJUyABLCfMsUseq6oKkZ7nF7iKr1U3un/p3w3M6cHEWpmlPYkd222MQ8E4/aatU8zffS m1Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=ZLrv7XiB31CYgQy686NY+c/cajh5RqkEfQmHjWEpDZo=; b=mcP9+HnJ6lv5WRpnMyiolXHsS3twtJatxZJB3XWRHqB/YqTs7WEekUzcmpklokVR4b zstWWN7SXFyhoBZdVrY9hSOHPW/LFIqff+nbowBbAONS6FX+7O9LOheRvCxw/PJUwkr8 UTys+HSYbYy/NMfXWa+/XNCL8zr+iiN6lxzobMxHs44Dbl19fCH6lq1JRkecpj0lVJiI cZaBVImd8kYjT1B3PrLEQldZeTBp1qulmotRBos2phz4KAsNU6aXjy0vfJbYpAycAZVz aOTJYubCFW3pAiAjcL1Ofqi8sTJUQPEYRtIr7lT7X55yWRa/MsQk6Fk9W3/92h0JB3c2 IO3Q== X-Gm-Message-State: AIVw111NJbZ62jzeETX/bbeVklCbf52JqCUtA1voJ/rY2T+Ma1GUi9aZ vrrO0MNAccaf3RftGLg= X-Received: by 10.237.35.239 with SMTP id k44mr19007971qtc.125.1499300689070; Wed, 05 Jul 2017 17:24:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 5 Jul 2017 14:23:59 -1000 Message-Id: <20170706002401.10507-10-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170706002401.10507-1-rth@twiddle.net> References: <20170706002401.10507-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::242 Subject: [Qemu-devel] [PATCH 09/11] target/sh4: Avoid a potential translator crash for malformed FPR64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno@clisp.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Produce valid, but nonsensical, code given an odd register index. Signed-off-by: Richard Henderson --- target/sh4/translate.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 05657a9..7f015c3 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -359,14 +359,18 @@ static void gen_delayed_conditional_jump(DisasContext= * ctx) gen_jump(ctx); } =20 -static inline void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) +/* Assumes lsb of (x) is always 0. */ +/* ??? Should the translator should signal an invalid opc? + In the meantime, using OR instead of PLUS to form the index of the + low register means we can't crash the translator for REG=3D=3D15. */ +static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { - tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]); + tcg_gen_concat_i32_i64(t, cpu_fregs[reg | 1], cpu_fregs[reg]); } =20 -static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) +static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { - tcg_gen_extr_i64_i32(cpu_fregs[reg + 1], cpu_fregs[reg], t); + tcg_gen_extr_i64_i32(cpu_fregs[reg | 1], cpu_fregs[reg], t); } =20 #define B3_0 (ctx->opcode & 0xf) @@ -385,7 +389,6 @@ static inline void gen_store_fpr64(DisasContext *ctx, T= CGv_i64 t, int reg) #define FREG(x) cpu_fregs[ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)] #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) #define XREG(x) FREG(XHACK(x)) -/* Assumes lsb of (x) is always 0 */ #define DREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)) =20 #define CHECK_NOT_DELAY_SLOT \ --=20 2.9.4 From nobody Wed Nov 5 08:02:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499301069557768.1376613014944; Wed, 5 Jul 2017 17:31:09 -0700 (PDT) Received: from localhost ([::1]:48656 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSuhI-0004tx-54 for importer@patchew.org; Wed, 05 Jul 2017 20:31:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59807) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSubF-0007ih-W9 for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSubF-0002UK-2R for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:53 -0400 Received: from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:36280) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dSubE-0002UC-U0 for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:52 -0400 Received: by mail-qk0-x243.google.com with SMTP id v143so639842qkb.3 for ; Wed, 05 Jul 2017 17:24:52 -0700 (PDT) Received: from bigtime.twiddle.net.com (rrcs-66-91-136-156.west.biz.rr.com. [66.91.136.156]) by smtp.gmail.com with ESMTPSA id u85sm371825qku.42.2017.07.05.17.24.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Jul 2017 17:24:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=loaGOXqQPSIwMsQbSfcyUWu+AfoCneWBOsKNgHULlnQ=; b=deUzxq1akeuT7eK+AgXJ4QZeKEWJQMxgqijS+VSX8MOtJtVFIUWhA7e04IyVr16Eiq CIyu6VuLaiyBLF4H7lHw7eYMHTqwTSIidZL1RNEsam/zpyLTcIhHRf8yFD9KcWjBRKpF WjZxNb0Co8bz/ZnveKCTYSZu79/kiweZ2//mrAhKi1NrEN9EKXib/t3OrNIlasVSICAo hroO3EknLt7xC5qcHmYsR3DJ23xf/0clt/zlU7ikRvm3iMTVXURN7gThFvm7rmWM3YqX KYe2pfJCyx6i9SjnUMCH0hw0yV6oN0zaC0D3QuziVG6q7f/IGF6ojSV76cwpb5UmqG3h bsgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=loaGOXqQPSIwMsQbSfcyUWu+AfoCneWBOsKNgHULlnQ=; b=URUerQBdIdN47p3ZHVzGxDEIr/OQjWXIrh8ehlfCjIDitWrimk0B8Qqro0VK4LcHrl KJSpS1ttNN7O3isH675h2N7N5VoFI5Nrk6I4NqKcxbHo0nhhjOufggn4eFFb9bu0Bndi wDhGCxAPLJW3BiuUMIIKuhvMuDSsxc3d8AL1f5qEtsCwB6C7fUuDHTW/GD87m6kNDfdx icv1XFPWhMSdIfqCobBSLRhnY9Eu2GG2n6iwNH4sZIXXv6nuNieLqicCi+KzUeujxXFf FSCuESVf27OERIAi3SbhFz7W/1lFL1+w6rEBzucPtT+lyS/7j5RDWI43xMdCZ735tjH1 0o6Q== X-Gm-Message-State: AKS2vOz+2VbRabfXB0tyJvIqXfXSr22rECwp1stxG9egWLhzPiXqr9x6 RTzzOOO8ip9/OA7nfZ8= X-Received: by 10.55.20.30 with SMTP id e30mr52941319qkh.51.1499300692270; Wed, 05 Jul 2017 17:24:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 5 Jul 2017 14:24:00 -1000 Message-Id: <20170706002401.10507-11-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170706002401.10507-1-rth@twiddle.net> References: <20170706002401.10507-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH 10/11] target/sh4: Hoist fp bank selection X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno@clisp.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/sh4/translate.c | 34 +++++++++++++++++++++++----------- 1 file changed, 23 insertions(+), 11 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 7f015c3..a45d0ee 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -37,6 +37,7 @@ typedef struct DisasContext { struct TranslationBlock *tb; TCGv *gregs; /* active bank */ TCGv *altregs; /* inactive, alternate, bank */ + TCGv *fregs; /* active bank */ target_ulong pc; uint16_t opcode; uint32_t tbflags; /* should stay unmodified during the TB translati= on */ @@ -72,7 +73,7 @@ static TCGv cpu_pc, cpu_ssr, cpu_spc, cpu_gbr; static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl; static TCGv cpu_pr, cpu_fpscr, cpu_fpul; static TCGv cpu_lock_addr, cpu_lock_value; -static TCGv cpu_fregs[32]; +static TCGv cpu_fregs[2][16]; =20 /* internal register indexes */ static TCGv cpu_flags, cpu_delayed_pc, cpu_delayed_cond; @@ -176,10 +177,18 @@ void sh4_translate_init(void) offsetof(CPUSH4State, lock_value), "_lock_value_"); =20 - for (i =3D 0; i < 32; i++) - cpu_fregs[i] =3D tcg_global_mem_new_i32(cpu_env, - offsetof(CPUSH4State, fregs[= i]), - fregnames[i]); + for (i =3D 0; i < 16; i++) { + cpu_fregs[0][i] + =3D tcg_global_mem_new_i32(cpu_env, + offsetof(CPUSH4State, fregs[i]), + fregnames[i]); + } + for (i =3D 16; i < 32; i++) { + cpu_fregs[1][i - 16] + =3D tcg_global_mem_new_i32(cpu_env, + offsetof(CPUSH4State, fregs[i]), + fregnames[i]); + } =20 done_init =3D 1; } @@ -365,12 +374,12 @@ static void gen_delayed_conditional_jump(DisasContext= * ctx) low register means we can't crash the translator for REG=3D=3D15. */ static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { - tcg_gen_concat_i32_i64(t, cpu_fregs[reg | 1], cpu_fregs[reg]); + tcg_gen_concat_i32_i64(t, ctx->fregs[reg | 1], ctx->fregs[reg]); } =20 static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { - tcg_gen_extr_i64_i32(cpu_fregs[reg | 1], cpu_fregs[reg], t); + tcg_gen_extr_i64_i32(ctx->fregs[reg | 1], ctx->fregs[reg], t); } =20 #define B3_0 (ctx->opcode & 0xf) @@ -386,10 +395,10 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i= 64 t, int reg) #define REG(x) ctx->gregs[x] #define ALTREG(x) ctx->altregs[x] =20 -#define FREG(x) cpu_fregs[ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)] -#define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) -#define XREG(x) FREG(XHACK(x)) -#define DREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)) +#define FREG(x) ctx->fregs[x] +#define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) +#define XREG(x) FREG(XHACK(x)) +#define DREG(x) (x) =20 #define CHECK_NOT_DELAY_SLOT \ if (ctx->envflags & DELAY_SLOT_MASK) { \ @@ -2230,6 +2239,9 @@ void gen_intermediate_code(CPUSH4State * env, struct = TranslationBlock *tb) ctx.gregs =3D cpu_gregs[bank]; ctx.altregs =3D cpu_gregs[bank ^ 1]; =20 + bank =3D (ctx.tbflags & FPSCR_FR) !=3D 0; + ctx.fregs =3D cpu_fregs[bank]; + max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; --=20 2.9.4 From nobody Wed Nov 5 08:02:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 14993010936180.05161403490410521; Wed, 5 Jul 2017 17:31:33 -0700 (PDT) Received: from localhost ([::1]:48657 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSuhg-0005DN-51 for importer@patchew.org; Wed, 05 Jul 2017 20:31:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59825) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSubJ-0007mB-Ff for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSubI-0002VE-Hp for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:57 -0400 Received: from mail-qt0-x242.google.com ([2607:f8b0:400d:c0d::242]:32818) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dSubI-0002V8-Cw for qemu-devel@nongnu.org; Wed, 05 Jul 2017 20:24:56 -0400 Received: by mail-qt0-x242.google.com with SMTP id c20so651639qte.0 for ; Wed, 05 Jul 2017 17:24:56 -0700 (PDT) Received: from bigtime.twiddle.net.com (rrcs-66-91-136-156.west.biz.rr.com. [66.91.136.156]) by smtp.gmail.com with ESMTPSA id u85sm371825qku.42.2017.07.05.17.24.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Jul 2017 17:24:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=mdZRNuchP419lEzUPzWqFSj2S6oApLJvlBmCIooTHYM=; b=EIP8s9GOyQKLPLQImLabAYsZP+MfMd2NXPdzZ9FrCd96aIdgRqlM4DesrlQLLjAka5 uk9kNOvv6JTq1ywswDMIGDv+88bS5LuASmwbDLiPyjQJ5d4GpOHFS0Xqxs29ONIRJUL4 z6/3PDOw5IHV7t/os+YlIDfvyALShpwm1HGJ0yE+TuH/w0/bdBl3F6nM5qrSXrkLjzoX /MoiGV846fevYpxWxXhirffN4WyAshEBhUfjzNHPZcYs3hb7/ul5sUP0hqtgD4b1YW+e 0XyzRDAtz7Fh7mbGAjdzbW+1vTlwc4e8CX+A0K1qAC2zoos/qCiwmxfyNDdSUB4EmNTf 0h8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=mdZRNuchP419lEzUPzWqFSj2S6oApLJvlBmCIooTHYM=; b=uBj0NDR2xAbY65RiUKH4m4BTkZyRTWKCnFKoASC8Mt4GAOkgKZUj0oigZ5u3HAQNm6 HW6xa+mVCmGaO2UaGf7QZspl1YRmEQIzdCWeD66RGvjwmJnGoxNDpDv6lqbDEdKGZh0P ZCX7qjnVNhdNdYjdI+J3msAr3tlE5FLuu1CMU+xR2t0a2BafIE3J5S2LfCrB+QQVEcby n50F1UFlqHxsXjrAluXYE62DLRT2zJArs76EuXq8fxsLgoywR2IrbZdncUrRyPZpLP6c 6fI4mBVBmQVuD+zFlb1+mp7v6LNrRLzJ3N5HVlSzZsBXLAMCJjtkjJVKsZtYUleWPGcE Syew== X-Gm-Message-State: AIVw112e+B+a8yMKtKDZEeIfKCQIaeXxz6xD0LKWHcagBdK+Ynqsjzio /fbhdzea30VhkrfjMHw= X-Received: by 10.200.44.87 with SMTP id e23mr30404954qta.123.1499300695753; Wed, 05 Jul 2017 17:24:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 5 Jul 2017 14:24:01 -1000 Message-Id: <20170706002401.10507-12-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170706002401.10507-1-rth@twiddle.net> References: <20170706002401.10507-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::242 Subject: [Qemu-devel] [PATCH 11/11] target/sh4: Eliminate DREG macro X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno@clisp.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/sh4/translate.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index a45d0ee..7e3de74 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -398,7 +398,6 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i64= t, int reg) #define FREG(x) ctx->fregs[x] #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) #define XREG(x) FREG(XHACK(x)) -#define DREG(x) (x) =20 #define CHECK_NOT_DELAY_SLOT \ if (ctx->envflags & DELAY_SLOT_MASK) { \ @@ -1128,8 +1127,8 @@ static void _decode_opc(DisasContext * ctx) break; /* illegal instruction */ fp0 =3D tcg_temp_new_i64(); fp1 =3D tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp0, DREG(B11_8)); - gen_load_fpr64(ctx, fp1, DREG(B7_4)); + gen_load_fpr64(ctx, fp0, B11_8); + gen_load_fpr64(ctx, fp1, B7_4); switch (ctx->opcode & 0xf00f) { case 0xf000: /* fadd Rm,Rn */ gen_helper_fadd_DT(fp0, cpu_env, fp0, fp1); @@ -1150,7 +1149,7 @@ static void _decode_opc(DisasContext * ctx) gen_helper_fcmp_gt_DT(cpu_env, fp0, fp1); return; } - gen_store_fpr64(ctx, fp0, DREG(B11_8)); + gen_store_fpr64(ctx, fp0, B11_8); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); } else { @@ -1740,7 +1739,7 @@ static void _decode_opc(DisasContext * ctx) break; /* illegal instruction */ fp =3D tcg_temp_new_i64(); gen_helper_float_DT(fp, cpu_env, cpu_fpul); - gen_store_fpr64(ctx, fp, DREG(B11_8)); + gen_store_fpr64(ctx, fp, B11_8); tcg_temp_free_i64(fp); } else { @@ -1754,7 +1753,7 @@ static void _decode_opc(DisasContext * ctx) if (ctx->opcode & 0x0100) break; /* illegal instruction */ fp =3D tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp, DREG(B11_8)); + gen_load_fpr64(ctx, fp, B11_8); gen_helper_ftrc_DT(cpu_fpul, cpu_env, fp); tcg_temp_free_i64(fp); } @@ -1774,9 +1773,9 @@ static void _decode_opc(DisasContext * ctx) if (ctx->opcode & 0x0100) break; /* illegal instruction */ TCGv_i64 fp =3D tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp, DREG(B11_8)); + gen_load_fpr64(ctx, fp, B11_8); gen_helper_fabs_DT(fp, fp); - gen_store_fpr64(ctx, fp, DREG(B11_8)); + gen_store_fpr64(ctx, fp, B11_8); tcg_temp_free_i64(fp); } else { gen_helper_fabs_FT(FREG(B11_8), FREG(B11_8)); @@ -1788,9 +1787,9 @@ static void _decode_opc(DisasContext * ctx) if (ctx->opcode & 0x0100) break; /* illegal instruction */ TCGv_i64 fp =3D tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp, DREG(B11_8)); + gen_load_fpr64(ctx, fp, B11_8); gen_helper_fsqrt_DT(fp, cpu_env, fp); - gen_store_fpr64(ctx, fp, DREG(B11_8)); + gen_store_fpr64(ctx, fp, B11_8); tcg_temp_free_i64(fp); } else { gen_helper_fsqrt_FT(FREG(B11_8), cpu_env, FREG(B11_8)); @@ -1816,7 +1815,7 @@ static void _decode_opc(DisasContext * ctx) { TCGv_i64 fp =3D tcg_temp_new_i64(); gen_helper_fcnvsd_FT_DT(fp, cpu_env, cpu_fpul); - gen_store_fpr64(ctx, fp, DREG(B11_8)); + gen_store_fpr64(ctx, fp, B11_8); tcg_temp_free_i64(fp); } return; @@ -1824,7 +1823,7 @@ static void _decode_opc(DisasContext * ctx) CHECK_FPU_ENABLED { TCGv_i64 fp =3D tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp, DREG(B11_8)); + gen_load_fpr64(ctx, fp, B11_8); gen_helper_fcnvds_DT_FT(cpu_fpul, cpu_env, fp); tcg_temp_free_i64(fp); } --=20 2.9.4