From nobody Mon Feb 9 14:50:40 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499151739667765.6228591546669; Tue, 4 Jul 2017 00:02:19 -0700 (PDT) Received: from localhost ([::1]:38961 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSHqk-0003qR-E1 for importer@patchew.org; Tue, 04 Jul 2017 03:02:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41846) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSHZa-0004U8-Tr for qemu-devel@nongnu.org; Tue, 04 Jul 2017 02:44:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSHZZ-0003CY-Lt for qemu-devel@nongnu.org; Tue, 04 Jul 2017 02:44:34 -0400 Received: from mx1.redhat.com ([209.132.183.28]:56218) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dSHZZ-0003CE-Cp for qemu-devel@nongnu.org; Tue, 04 Jul 2017 02:44:33 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 4CB9B80462 for ; Tue, 4 Jul 2017 06:44:32 +0000 (UTC) Received: from lemon.redhat.com (ovpn-12-33.pek2.redhat.com [10.72.12.33]) by smtp.corp.redhat.com (Postfix) with ESMTP id B883263F77; Tue, 4 Jul 2017 06:44:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 4CB9B80462 Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=famz@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 4CB9B80462 From: Fam Zheng To: qemu-devel@nongnu.org Date: Tue, 4 Jul 2017 14:43:46 +0800 Message-Id: <20170704064347.7022-20-famz@redhat.com> In-Reply-To: <20170704064347.7022-1-famz@redhat.com> References: <20170704064347.7022-1-famz@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Tue, 04 Jul 2017 06:44:32 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v3 19/20] cpu: Convert to DEFINE_PROP_LINK X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Igor Mammedov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Fam Zheng --- cpus.c | 5 +++-- exec.c | 30 ++++++++++++++++-------------- include/qom/cpu.h | 4 +++- qom/cpu.c | 1 + target/arm/cpu.c | 6 +++--- target/i386/cpu.c | 5 +++-- 6 files changed, 29 insertions(+), 22 deletions(-) diff --git a/cpus.c b/cpus.c index 14bb8d5..708ee78 100644 --- a/cpus.c +++ b/cpus.c @@ -1764,8 +1764,9 @@ void qemu_init_vcpu(CPUState *cpu) /* If the target cpu hasn't set up any address spaces itself, * give it the default one. */ - AddressSpace *as =3D address_space_init_shareable(cpu->memory, - "cpu-memory"); + AddressSpace *as =3D + address_space_init_shareable(MEMORY_REGION(cpu->memory), + "cpu-memory"); cpu->num_ases =3D 1; cpu_address_space_init(cpu, as, 0); } diff --git a/exec.c b/exec.c index 42ad1ea..26a4f0f 100644 --- a/exec.c +++ b/exec.c @@ -27,6 +27,7 @@ #include "exec/target_page.h" #include "tcg.h" #include "hw/qdev-core.h" +#include "hw/qdev-properties.h" #if !defined(CONFIG_USER_ONLY) #include "hw/boards.h" #include "hw/xen/xen.h" @@ -730,6 +731,19 @@ void cpu_exec_unrealizefn(CPUState *cpu) } } =20 +Property cpu_common_props[] =3D { +#ifndef CONFIG_USER_ONLY + /* Create a memory property for softmmu CPU object, + * so users can wire up its memory. (This can't go in qom/cpu.c + * because that file is compiled only once for both user-mode + * and system builds.) The default if no link is set up is to use + * the system address space. + */ + DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION), +#endif + DEFINE_PROP_END_OF_LIST(), +}; + void cpu_exec_initfn(CPUState *cpu) { cpu->as =3D NULL; @@ -737,20 +751,8 @@ void cpu_exec_initfn(CPUState *cpu) =20 #ifndef CONFIG_USER_ONLY cpu->thread_id =3D qemu_get_thread_id(); - - /* This is a softmmu CPU object, so create a property for it - * so users can wire up its memory. (This can't go in qom/cpu.c - * because that file is compiled only once for both user-mode - * and system builds.) The default if no link is set up is to use - * the system address space. - */ - object_property_add_link(OBJECT(cpu), "memory", TYPE_MEMORY_REGION, - (Object **)&cpu->memory, - qdev_prop_allow_set_link_before_realize, - OBJ_PROP_LINK_UNREF_ON_RELEASE, - &error_abort); - cpu->memory =3D system_memory; - object_ref(OBJECT(cpu->memory)); + cpu->memory =3D OBJECT(system_memory); + object_ref(cpu->memory); #endif } =20 diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 2fe7cff..9857781 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -342,7 +342,8 @@ struct CPUState { CPUAddressSpace *cpu_ases; int num_ases; AddressSpace *as; - MemoryRegion *memory; + /* Memory region pointer to be filled by link property */ + Object *memory; =20 void *env_ptr; /* CPUArchState */ =20 @@ -1010,6 +1011,7 @@ AddressSpace *cpu_get_address_space(CPUState *cpu, in= t asidx); =20 void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) GCC_FMT_ATTR(2, 3); +extern Property cpu_common_props[]; void cpu_exec_initfn(CPUState *cpu); void cpu_exec_realizefn(CPUState *cpu, Error **errp); void cpu_exec_unrealizefn(CPUState *cpu); diff --git a/qom/cpu.c b/qom/cpu.c index 585419b..071551c 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -446,6 +446,7 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) set_bit(DEVICE_CATEGORY_CPU, dc->categories); dc->realize =3D cpu_common_realizefn; dc->unrealize =3D cpu_common_unrealizefn; + dc->props =3D cpu_common_props; /* * Reason: CPUs still need special care by board code: wiring up * IRQs, adding reset handlers, halting non-first CPUs, ... diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 28a9141..9b5968b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -817,14 +817,14 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) AddressSpace *as; =20 if (!cpu->secure_memory) { - cpu->secure_memory =3D cs->memory; + cpu->secure_memory =3D MEMORY_REGION(cs->memory); } - as =3D address_space_init_shareable(cpu->secure_memory, + as =3D address_space_init_shareable(MEMORY_REGION(cpu->secure_memo= ry), "cpu-secure-memory"); cpu_address_space_init(cs, as, ARMASIdx_S); } cpu_address_space_init(cs, - address_space_init_shareable(cs->memory, + address_space_init_shareable(MEMORY_REGION(cs->= memory), "cpu-memory"), ARMASIdx_NS); #endif diff --git a/target/i386/cpu.c b/target/i386/cpu.c index fce277b..4f1c9fa 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3615,8 +3615,9 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) =20 #ifndef CONFIG_USER_ONLY if (tcg_enabled()) { - AddressSpace *as_normal =3D address_space_init_shareable(cs->memor= y, - "cpu-memory= "); + AddressSpace *as_normal =3D + address_space_init_shareable(MEMORY_REGION(cs->memory), + "cpu-memory"); AddressSpace *as_smm =3D g_new(AddressSpace, 1); =20 cpu->cpu_as_mem =3D g_new(MemoryRegion, 1); --=20 2.9.4