From nobody Wed May 8 01:59:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499099158310707.4609208740598; Mon, 3 Jul 2017 09:25:58 -0700 (PDT) Received: from localhost ([::1]:36237 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dS4Ae-000484-TS for importer@patchew.org; Mon, 03 Jul 2017 12:25:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48946) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dS48t-0002ot-RY for qemu-devel@nongnu.org; Mon, 03 Jul 2017 12:24:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dS48q-00010n-Hc for qemu-devel@nongnu.org; Mon, 03 Jul 2017 12:24:07 -0400 Received: from mout.kundenserver.de ([212.227.17.24]:63259) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dS48q-00010L-68 for qemu-devel@nongnu.org; Mon, 03 Jul 2017 12:24:04 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue104 [212.227.15.183]) with ESMTPSA (Nemesis) id 0MN4ps-1dLTUy1Wm0-006iwn; Mon, 03 Jul 2017 18:23:32 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 3 Jul 2017 18:23:25 +0200 Message-Id: <20170703162328.24474-2-laurent@vivier.eu> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170703162328.24474-1-laurent@vivier.eu> References: <20170703162328.24474-1-laurent@vivier.eu> X-Provags-ID: V03:K0:feMTo8Yi6WfS05YzIdAn2nCFDZbkWFxHDceixQGlEqMK8AaXPLS Pya7cyy4zpLYJYCDnUdS4CDUvOImF0c19JLCB8YNktee99qms5WBLTctv5JNjKYpSXwKtAs 8IDKOpD4tmQuQDUGLLzJWv2n9ISc5Vqz92TecJDp/smPY0BjPLwAuPCuK6s6ypAzi8X2JOv 7rD0DrcL9dUS+LxeeGkWw== X-UI-Out-Filterresults: notjunk:1;V01:K0:D5sMS+OHFhU=:vN5wiyc+nfZN9V3xSIoEyL FQa9ZSVYEv3hXeJReSnsNxG0hAybWBJlxeP/VwIkDgRW8Z3lSGDtoGvyVQxin/wxRNTXkFLg8 U7yg8yAG1Uv/aHLUXH6Hwnt+zPSzGkTI+4ep/YNKke4P/ZISn2Xvr+iieqx/kvF5VA5Xghu7b nz+qBK+HNb75DEkObeACHxM32CbIo2Qdfb0HNgRt9WcmFus+T9dyVXBVougzMMzzp6VksLyJl pnJ67C/Rm/BUYQHx31W/OnizUwUYxj23R8lbqN7MlN5bHEwGxQh+sprvFDOHlK4RUWfjsCQPM xDTqWv8zeQ6brZdnfwYUdlUT4DRRjYVg7tIlU5Gf0W69LAtVr03Fww3r7XChMKVMXyd3/Scpx DELVU/srxUcTHA3xhdR9sDl9w3NR1ZfjAw/Tpy/yFSXtToUFxYiT37OPJa0IqCQoWNM68hI7a jizlhqlwG+F44gUTIdbyBttwWe7fGn0uPrDs5x8FHygp5TtGZlo0XJV0jzyl90UK0Bo38Bf7L L7zYpksUSzXBlK4HQlxQfUcoZ7Fn5/gA2YqoxlZlKUg3pn1yfCrF5AJRtFCt+/ld5GPlCuiGE Rcp6IFXrybOgZfezy3RRjYAmxkBRMvhnREkHMHsOR+WKGnFRL+lut77Ngm2sTOH2kLHZ3PJP9 3N/QTdYZsLBEqL+/IDnULfptoP4E3gNe/sMBlD6sFqze/amGw1d+bNaugBqeUJuH8kbc= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.17.24 Subject: [Qemu-devel] [PATCH 1/4] softfloat: use floatx80_infinity in softfloat X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since f3218a8 ("softfloat: add floatx80 constants") floatx80_infinity is defined but never used. This patch updates floatx80 functions to use this definition. This allows to define a different default Infinity value on m68k: the m68k FPU defines infinity with all bits set to zero in the mantissa. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- fpu/softfloat-specialize.h | 14 ++++++++++++++ fpu/softfloat.c | 38 ++++++++++++++++++++++++++------------ include/fpu/softfloat.h | 9 +++++++-- 3 files changed, 47 insertions(+), 14 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index de2c5d5..1cb3502 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -178,6 +178,20 @@ floatx80 floatx80_default_nan(float_status *status) } =20 /*------------------------------------------------------------------------= ---- +| The pattern for a default generated extended double-precision inf. +*-------------------------------------------------------------------------= ---*/ + +#define floatx80_infinity_high 0x7FFF +#if defined(TARGET_M68K) +#define floatx80_infinity_low LIT64(0x0000000000000000) +#else +#define floatx80_infinity_low LIT64(0x8000000000000000) +#endif + +const floatx80 floatx80_infinity + =3D make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low); + +/*------------------------------------------------------------------------= ---- | The pattern for a default generated quadruple-precision NaN. *-------------------------------------------------------------------------= ---*/ float128 float128_default_nan(float_status *status) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 433c5da..2355403 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -913,7 +913,9 @@ static floatx80 roundAndPackFloatx80(int8_t roundingPre= cision, flag zSign, ) { return packFloatx80( zSign, 0x7FFE, ~ roundMask ); } - return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 = ) ); + return packFloatx80(zSign, + floatx80_infinity_high, + floatx80_infinity_low); } if ( zExp <=3D 0 ) { isTiny =3D @@ -1885,7 +1887,9 @@ floatx80 float32_to_floatx80(float32 a, float_status = *status) if (aSig) { return commonNaNToFloatx80(float32ToCommonNaN(a, status), stat= us); } - return packFloatx80( aSign, 0x7FFF, LIT64( 0x8000000000000000 ) ); + return packFloatx80(aSign, + floatx80_infinity_high, + floatx80_infinity_low); } if ( aExp =3D=3D 0 ) { if ( aSig =3D=3D 0 ) return packFloatx80( aSign, 0, 0 ); @@ -3666,7 +3670,9 @@ floatx80 float64_to_floatx80(float64 a, float_status = *status) if (aSig) { return commonNaNToFloatx80(float64ToCommonNaN(a, status), stat= us); } - return packFloatx80( aSign, 0x7FFF, LIT64( 0x8000000000000000 ) ); + return packFloatx80(aSign, + floatx80_infinity_high, + floatx80_infinity_low); } if ( aExp =3D=3D 0 ) { if ( aSig =3D=3D 0 ) return packFloatx80( aSign, 0, 0 ); @@ -4927,8 +4933,8 @@ int64_t floatx80_to_int64(floatx80 a, float_status *s= tatus) if ( shiftCount ) { float_raise(float_flag_invalid, status); if ( ! aSign - || ( ( aExp =3D=3D 0x7FFF ) - && ( aSig !=3D LIT64( 0x8000000000000000 ) ) ) + || ((aExp =3D=3D floatx80_infinity_high) + && (aSig !=3D floatx80_infinity_low)) ) { return LIT64( 0x7FFFFFFFFFFFFFFF ); } @@ -5235,7 +5241,9 @@ static floatx80 addFloatx80Sigs(floatx80 a, floatx80 = b, flag zSign, if ((uint64_t)(bSig << 1)) { return propagateFloatx80NaN(a, b, status); } - return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 = ) ); + return packFloatx80(zSign, + floatx80_infinity_high, + floatx80_infinity_low); } if ( aExp =3D=3D 0 ) ++expDiff; shift64ExtraRightJamming( aSig, 0, - expDiff, &aSig, &zSig1 ); @@ -5310,7 +5318,8 @@ static floatx80 subFloatx80Sigs(floatx80 a, floatx80 = b, flag zSign, if ((uint64_t)(bSig << 1)) { return propagateFloatx80NaN(a, b, status); } - return packFloatx80( zSign ^ 1, 0x7FFF, LIT64( 0x8000000000000000 = ) ); + return packFloatx80(zSign ^ 1, floatx80_infinity_high, + floatx80_infinity_low); } if ( aExp =3D=3D 0 ) ++expDiff; shift128RightJamming( aSig, 0, - expDiff, &aSig, &zSig1 ); @@ -5415,7 +5424,8 @@ floatx80 floatx80_mul(floatx80 a, floatx80 b, float_s= tatus *status) return propagateFloatx80NaN(a, b, status); } if ( ( bExp | bSig ) =3D=3D 0 ) goto invalid; - return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) ); + return packFloatx80(zSign, floatx80_infinity_high, + floatx80_infinity_low); } if ( bExp =3D=3D 0x7FFF ) { if ((uint64_t)(bSig << 1)) { @@ -5426,7 +5436,8 @@ floatx80 floatx80_mul(floatx80 a, floatx80 b, float_s= tatus *status) float_raise(float_flag_invalid, status); return floatx80_default_nan(status); } - return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) ); + return packFloatx80(zSign, floatx80_infinity_high, + floatx80_infinity_low); } if ( aExp =3D=3D 0 ) { if ( aSig =3D=3D 0 ) return packFloatx80( zSign, 0, 0 ); @@ -5480,7 +5491,8 @@ floatx80 floatx80_div(floatx80 a, floatx80 b, float_s= tatus *status) } goto invalid; } - return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) ); + return packFloatx80(zSign, floatx80_infinity_high, + floatx80_infinity_low); } if ( bExp =3D=3D 0x7FFF ) { if ((uint64_t)(bSig << 1)) { @@ -5496,7 +5508,8 @@ floatx80 floatx80_div(floatx80 a, floatx80 b, float_s= tatus *status) return floatx80_default_nan(status); } float_raise(float_flag_divbyzero, status); - return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 = ) ); + return packFloatx80(zSign, floatx80_infinity_high, + floatx80_infinity_low); } normalizeFloatx80Subnormal( bSig, &bExp, &bSig ); } @@ -6319,7 +6332,8 @@ floatx80 float128_to_floatx80(float128 a, float_statu= s *status) if ( aSig0 | aSig1 ) { return commonNaNToFloatx80(float128ToCommonNaN(a, status), sta= tus); } - return packFloatx80( aSign, 0x7FFF, LIT64( 0x8000000000000000 ) ); + return packFloatx80(aSign, floatx80_infinity_high, + floatx80_infinity_low); } if ( aExp =3D=3D 0 ) { if ( ( aSig0 | aSig1 ) =3D=3D 0 ) return packFloatx80( aSign, 0, 0= ); diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index d9689ec..464a0f7 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -619,6 +619,11 @@ float64 floatx80_to_float64(floatx80, float_status *st= atus); float128 floatx80_to_float128(floatx80, float_status *status); =20 /*------------------------------------------------------------------------= ---- +| The pattern for an extended double-precision inf. +*-------------------------------------------------------------------------= ---*/ +extern const floatx80 floatx80_infinity; + +/*------------------------------------------------------------------------= ---- | Software IEC/IEEE extended double-precision operations. *-------------------------------------------------------------------------= ---*/ floatx80 floatx80_round(floatx80 a, float_status *status); @@ -658,7 +663,8 @@ static inline floatx80 floatx80_chs(floatx80 a) =20 static inline int floatx80_is_infinity(floatx80 a) { - return (a.high & 0x7fff) =3D=3D 0x7fff && a.low =3D=3D 0x8000000000000= 000LL; + return (a.high & 0x7fff) =3D=3D floatx80_infinity.high && + a.low =3D=3D floatx80_infinity.low; } =20 static inline int floatx80_is_neg(floatx80 a) @@ -701,7 +707,6 @@ static inline bool floatx80_invalid_encoding(floatx80 a) #define floatx80_ln2 make_floatx80(0x3ffe, 0xb17217f7d1cf79acLL) #define floatx80_pi make_floatx80(0x4000, 0xc90fdaa22168c235LL) #define floatx80_half make_floatx80(0x3ffe, 0x8000000000000000LL) -#define floatx80_infinity make_floatx80(0x7fff, 0x8000000000000000LL) =20 /*------------------------------------------------------------------------= ---- | The pattern for a default generated extended double-precision NaN. --=20 2.9.4 From nobody Wed May 8 01:59:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499099261814891.5413023512232; Mon, 3 Jul 2017 09:27:41 -0700 (PDT) Received: from localhost ([::1]:36241 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dS4CK-0005ge-7D for importer@patchew.org; Mon, 03 Jul 2017 12:27:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48927) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dS48s-0002mK-8u for qemu-devel@nongnu.org; Mon, 03 Jul 2017 12:24:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dS48n-0000z4-Hd for qemu-devel@nongnu.org; Mon, 03 Jul 2017 12:24:06 -0400 Received: from mout.kundenserver.de ([212.227.17.10]:52759) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dS48n-0000xT-2L for qemu-devel@nongnu.org; Mon, 03 Jul 2017 12:24:01 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue104 [212.227.15.183]) with ESMTPSA (Nemesis) id 0MVd8x-1dDOFG0VbD-00YwX4; Mon, 03 Jul 2017 18:23:33 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 3 Jul 2017 18:23:26 +0200 Message-Id: <20170703162328.24474-3-laurent@vivier.eu> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170703162328.24474-1-laurent@vivier.eu> References: <20170703162328.24474-1-laurent@vivier.eu> X-Provags-ID: V03:K0:VYuqR86gdl4LAbs2XIHpZOk2OAkdH0zdu24jrG5VYm8ajST+99N CropqbHp1D8wFhQTdtb+qqDpQBnSCn0vx2P9DWU73G9p/Lk+fwqnBLop+ouNSGNeWkV/8up h4KXRHeBTU8VJEeqmK8kfU/LiTaPhuvAtFZpox6cZBum3KjI6ZXmfk+Ia5h6EviSY9UGOeh RMcm5p7TqlNrFQawBaHdw== X-UI-Out-Filterresults: notjunk:1;V01:K0:J/sPLi4hh8o=:3zQrOopiC+VNKQtTnp64zO C1YEci5hkSVLI+0838hT7+mf7+f/kEoOBsnlkS6wXcVw4IP4AgCaielRBM8Nw/2EtX5f/wA8T Cpfmjk/9AtED5SVxzF9/miOn1QAaO+BfMgANSIVcIMG4a66mECVwXCS9uvehfv1f/B3hpilNe 4u7Wx0Rz/DZ3/1X1DrJ+xTaqeqS9s6+0N/I+tfZSwtezb43mtnXLcUAFnibg/mWA5wdTuZE6p OoQb1bxwpjMR1HVPBmFo0jq0rbOqESWwL6Bk+kt+zLfSwvllJIgfhUeP/3fTvpjf21fRFRr/j A/nqwMb/JSir6Nxnz5TR9t8wyN+SKLLF+lPJKRWuGdfl1MdQ6x6YUFhdJOcO4Ldv7MYjosHcG 9jROE0JLHxcjB0UK8ANBoDguRejgvFP0KOcKZ8S9kcUxZODrWmLRV960FVGRqrGXlJqNpcL18 ds7ZPWQKByY3IKUfTJSJyXaJcf1jFS1wdMce5PCBB5UXQccUa7k6yXaTAfl15ZGyU/84VQ8a6 BFXdKjGjHS12XjKEv8P4hCiEQurtlmOWmyQ1GQ27yxSEyO+w8yf4+Z5cQ8usyUVKIxxxGT6Yw 4QEZsZCtaHFaJFTSI8Mqsb6UzsecGQHpNziM9Pv4DOn8QEO8z+0pPawcWATU1QurJMXsQvEde /SE+mi0GBx41hBjT1gY6qCtnf8Nz+JXX8jSOithfx3q9OgoYYkkh11px33ShFh82Lv4I= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.17.10 Subject: [Qemu-devel] [PATCH 2/4] target/m68k: add FPU trigonometric instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add fsinh, flognp1, ftanh, fatan, fasin, fatanh, fsin, ftan, fetox, ftwotox, ftentox, flogn, flog10, facos, fcos, fsincos. As softfloat library does not provide these functions, we use the libm of the host. Signed-off-by: Laurent Vivier --- target/m68k/cpu.h | 1 + target/m68k/fpu_helper.c | 228 +++++++++++++++++++++++++++++++++++++++++++= ++++ target/m68k/helper.h | 17 ++++ target/m68k/translate.c | 73 +++++++++++---- 4 files changed, 304 insertions(+), 15 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 38a7e11..f8f4dd5 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -173,6 +173,7 @@ uint32_t cpu_m68k_get_ccr(CPUM68KState *env); void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val); =20 +long double floatx80_to_ldouble(floatx80 val); =20 /* Instead of computing the condition codes after each m68k instruction, * QEMU just stores one operand (called CC_SRC), the result diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index bdfc537..2b07cb9 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -23,6 +23,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include =20 /* Undefined offsets may be different on various FPU. * On 68040 they return 0.0 (floatx80_zero) @@ -508,3 +509,230 @@ uint32_t HELPER(fmovemd_ld_postinc)(CPUM68KState *env= , uint32_t addr, { return fmovem_postinc(env, addr, mask, cpu_ld_float64_ra); } + +long double floatx80_to_ldouble(floatx80 val) +{ + long double mantissa; + int32_t exp; + uint8_t sign; + + if (floatx80_is_infinity(val)) { + if (floatx80_is_neg(val)) { + return -__builtin_infl(); + } + return __builtin_infl(); + } + if (floatx80_is_any_nan(val)) { + char low[20]; + sprintf(low, "0x%016"PRIx64, val.low); + return nanl(low); + } + + exp =3D (val.high & 0x7fff) - (0x3ffe + 64); + sign =3D val.high >> 15; + mantissa =3D (long double)val.low; + if (sign) { + mantissa =3D -mantissa; + } + + return ldexpl(mantissa, exp); +} + +static floatx80 ldouble_to_floatx80(long double val, float_status *status) +{ + floatx80 res; + long double mantissa; + int exp; + + if (isinf(val)) { + res =3D floatx80_infinity; + if (isinf(val) < 0) { + res =3D floatx80_chs(res); + } + return res; + } + if (isnan(val)) { + res.high =3D floatx80_default_nan(NULL).high; + res.low =3D *(uint64_t *)&val; /* FIXME */ + return res; + } + + mantissa =3D frexpl(val, &exp); + res.high =3D exp + 0x3ffe; + if (mantissa < 0) { + res =3D floatx80_chs(res); + mantissa =3D -mantissa; + } + res.low =3D (uint64_t)ldexpl(mantissa, 64); + + return floatx80_round(res, status); +} + +void HELPER(fsinh)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + long double d; + + d =3D sinhl(floatx80_to_ldouble(val->d)); + res->d =3D ldouble_to_floatx80(d, &env->fp_status); +} + +void HELPER(flognp1)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + long double d; + + d =3D logl(floatx80_to_ldouble(val->d) + 1.0); + + res->d =3D ldouble_to_floatx80(d, &env->fp_status); +} + +void HELPER(fln)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + long double d; + + d =3D logl(floatx80_to_ldouble(val->d)); + + res->d =3D ldouble_to_floatx80(d, &env->fp_status); +} + +void HELPER(flog10)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + long double d; + + d =3D log10l(floatx80_to_ldouble(val->d)); + + res->d =3D ldouble_to_floatx80(d, &env->fp_status); +} + +void HELPER(fatan)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + long double d; + + d =3D atanl(floatx80_to_ldouble(val->d)); + res->d =3D ldouble_to_floatx80(d, &env->fp_status); +} + +void HELPER(fasin)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + long double d; + + d =3D floatx80_to_ldouble(val->d); + if (d < -1.0 || d > 1.0) { + res->d =3D floatx80_default_nan(NULL); + return; + } + + res->d =3D ldouble_to_floatx80(asinl(d), &env->fp_status); +} + +void HELPER(fatanh)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + long double d; + + d =3D floatx80_to_ldouble(val->d); + if (d < -1.0 || d > 1.0) { + res->d =3D floatx80_default_nan(NULL); + return; + } + + d =3D atanhl(d); + res->d =3D ldouble_to_floatx80(d, &env->fp_status); +} + +void HELPER(fsin)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + long double d; + + d =3D sinl(floatx80_to_ldouble(val->d)); + res->d =3D ldouble_to_floatx80(d, &env->fp_status); +} + +void HELPER(ftanh)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + long double d; + + d =3D tanhl(floatx80_to_ldouble(val->d)); + + res->d =3D ldouble_to_floatx80(d, &env->fp_status); +} + +void HELPER(ftan)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + long double d; + + d =3D tanl(floatx80_to_ldouble(val->d)); + + res->d =3D ldouble_to_floatx80(d, &env->fp_status); +} + +void HELPER(fexp)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + long double d; + + d =3D expl(floatx80_to_ldouble(val->d)); + + res->d =3D ldouble_to_floatx80(d, &env->fp_status); +} + +void HELPER(fexp2)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + long double d; + + d =3D exp2l(floatx80_to_ldouble(val->d)); + + res->d =3D ldouble_to_floatx80(d, &env->fp_status); +} + +void HELPER(fexp10)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + long double d; + + d =3D exp10l(floatx80_to_ldouble(val->d)); + + res->d =3D ldouble_to_floatx80(d, &env->fp_status); +} + +void HELPER(fcosh)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + long double d; + + d =3D coshl(floatx80_to_ldouble(val->d)); + + res->d =3D ldouble_to_floatx80(d, &env->fp_status); +} + +void HELPER(facos)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + long double d; + + d =3D floatx80_to_ldouble(val->d); + if (d < -1.0 || d > 1.0) { + res->d =3D floatx80_default_nan(NULL); + return; + } + + d =3D acosl(d); + res->d =3D ldouble_to_floatx80(d, &env->fp_status); +} + +void HELPER(fcos)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + long double d; + + d =3D cosl(floatx80_to_ldouble(val->d)); + + res->d =3D ldouble_to_floatx80(d, &env->fp_status); +} + +void HELPER(fsincos)(CPUM68KState *env, FPReg *res0, FPReg *res1, FPReg *v= al) +{ + long double dsin, dcos; + + sincosl(floatx80_to_ldouble(val->d), &dsin, &dcos); + + /* If res0 and res1 specify the same floating-point data register, + * the sine result is stored in the register, and the cosine + * result is discarded. + */ + res1->d =3D ldouble_to_floatx80(dcos, &env->fp_status); + res0->d =3D ldouble_to_floatx80(dsin, &env->fp_status); +} diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 475a1f2..302b6c0 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -60,6 +60,23 @@ DEF_HELPER_3(fmovemx_ld_postinc, i32, env, i32, i32) DEF_HELPER_3(fmovemd_st_predec, i32, env, i32, i32) DEF_HELPER_3(fmovemd_st_postinc, i32, env, i32, i32) DEF_HELPER_3(fmovemd_ld_postinc, i32, env, i32, i32) +DEF_HELPER_3(fsinh, void, env, fp, fp) +DEF_HELPER_3(flognp1, void, env, fp, fp) +DEF_HELPER_3(fatan, void, env, fp, fp) +DEF_HELPER_3(fasin, void, env, fp, fp) +DEF_HELPER_3(fatanh, void, env, fp, fp) +DEF_HELPER_3(fsin, void, env, fp, fp) +DEF_HELPER_3(ftanh, void, env, fp, fp) +DEF_HELPER_3(ftan, void, env, fp, fp) +DEF_HELPER_3(fexp, void, env, fp, fp) +DEF_HELPER_3(fexp2, void, env, fp, fp) +DEF_HELPER_3(fexp10, void, env, fp, fp) +DEF_HELPER_3(fln, void, env, fp, fp) +DEF_HELPER_3(flog10, void, env, fp, fp) +DEF_HELPER_3(fcosh, void, env, fp, fp) +DEF_HELPER_3(facos, void, env, fp, fp) +DEF_HELPER_3(fcos, void, env, fp, fp) +DEF_HELPER_4(fsincos, void, env, fp, fp, fp) =20 DEF_HELPER_3(mac_move, void, env, i32, i32) DEF_HELPER_3(macmulf, i64, env, i32, i32) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 3a519b7..8a712b3 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4640,6 +4640,9 @@ DISAS_INSN(fpu) case 1: /* fint */ gen_helper_firound(cpu_env, cpu_dest, cpu_src); break; + case 2: /* fsinh */ + gen_helper_fsinh(cpu_env, cpu_dest, cpu_src); + break; case 3: /* fintrz */ gen_helper_fitrunc(cpu_env, cpu_dest, cpu_src); break; @@ -4652,6 +4655,42 @@ DISAS_INSN(fpu) case 0x45: /* fdsqrt */ gen_helper_fdsqrt(cpu_env, cpu_dest, cpu_src); break; + case 0x06: /* flognp1 */ + gen_helper_flognp1(cpu_env, cpu_dest, cpu_src); + break; + case 0x09: /* ftanh */ + gen_helper_ftanh(cpu_env, cpu_dest, cpu_src); + break; + case 0x0a: /* fatan */ + gen_helper_fatan(cpu_env, cpu_dest, cpu_src); + break; + case 0x0c: /* fasin */ + gen_helper_fasin(cpu_env, cpu_dest, cpu_src); + break; + case 0x0d: /* fatanh */ + gen_helper_fatanh(cpu_env, cpu_dest, cpu_src); + break; + case 0x0e: /* fsin */ + gen_helper_fsin(cpu_env, cpu_dest, cpu_src); + break; + case 0x0f: /* ftan */ + gen_helper_ftan(cpu_env, cpu_dest, cpu_src); + break; + case 0x10: /* fetox */ + gen_helper_fexp(cpu_env, cpu_dest, cpu_src); + break; + case 0x11: /* ftwotox */ + gen_helper_fexp2(cpu_env, cpu_dest, cpu_src); + break; + case 0x12: /* ftentox */ + gen_helper_fexp10(cpu_env, cpu_dest, cpu_src); + break; + case 0x14: /* flogn */ + gen_helper_fln(cpu_env, cpu_dest, cpu_src); + break; + case 0x15: /* flog10 */ + gen_helper_flog10(cpu_env, cpu_dest, cpu_src); + break; case 0x18: /* fabs */ gen_helper_fabs(cpu_env, cpu_dest, cpu_src); break; @@ -4661,6 +4700,9 @@ DISAS_INSN(fpu) case 0x5c: /* fdabs */ gen_helper_fdabs(cpu_env, cpu_dest, cpu_src); break; + case 0x19: /* fcosh */ + gen_helper_fcosh(cpu_env, cpu_dest, cpu_src); + break; case 0x1a: /* fneg */ gen_helper_fneg(cpu_env, cpu_dest, cpu_src); break; @@ -4670,6 +4712,12 @@ DISAS_INSN(fpu) case 0x5e: /* fdneg */ gen_helper_fdneg(cpu_env, cpu_dest, cpu_src); break; + case 0x1c: /* facos */ + gen_helper_facos(cpu_env, cpu_dest, cpu_src); + break; + case 0x1d: /* fcos */ + gen_helper_fcos(cpu_env, cpu_dest, cpu_src); + break; case 0x20: /* fdiv */ gen_helper_fdiv(cpu_env, cpu_dest, cpu_src, cpu_dest); break; @@ -4712,6 +4760,14 @@ DISAS_INSN(fpu) case 0x6c: /* fdsub */ gen_helper_fdsub(cpu_env, cpu_dest, cpu_src, cpu_dest); break; + case 0x30: case 0x31: case 0x32: + case 0x33: case 0x34: case 0x35: + case 0x36: case 0x37: { + TCGv_ptr cpu_dest2 =3D gen_fp_ptr(REG(ext, 0)); + gen_helper_fsincos(cpu_env, cpu_dest, cpu_dest2, cpu_src); + tcg_temp_free_ptr(cpu_dest2); + } + break; case 0x38: /* fcmp */ gen_helper_fcmp(cpu_env, cpu_src, cpu_dest); return; @@ -5626,18 +5682,6 @@ void gen_intermediate_code(CPUM68KState *env, Transl= ationBlock *tb) tb->icount =3D num_insns; } =20 -static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_= t low) -{ - floatx80 a =3D { .high =3D high, .low =3D low }; - union { - float64 f64; - double d; - } u; - - u.f64 =3D floatx80_to_float64(a, &env->fp_status); - return u.d; -} - void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprin= tf, int flags) { @@ -5647,11 +5691,10 @@ void m68k_cpu_dump_state(CPUState *cs, FILE *f, fpr= intf_function cpu_fprintf, uint16_t sr; for (i =3D 0; i < 8; i++) { cpu_fprintf(f, "D%d =3D %08x A%d =3D %08x " - "F%d =3D %04x %016"PRIx64" (%12g)\n", + "F%d =3D %04x %016"PRIx64" (%12Lg)\n", i, env->dregs[i], i, env->aregs[i], i, env->fregs[i].l.upper, env->fregs[i].l.lower, - floatx80_to_double(env, env->fregs[i].l.upper, - env->fregs[i].l.lower)); + floatx80_to_ldouble(env->fregs[i].d)); } cpu_fprintf (f, "PC =3D %08x ", env->pc); sr =3D env->sr | cpu_m68k_get_ccr(env); --=20 2.9.4 From nobody Wed May 8 01:59:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499099136689671.4202858118549; Mon, 3 Jul 2017 09:25:36 -0700 (PDT) Received: from localhost ([::1]:36234 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dS4AJ-0003qG-Ac for importer@patchew.org; Mon, 03 Jul 2017 12:25:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48887) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dS48m-0002ij-4R for qemu-devel@nongnu.org; Mon, 03 Jul 2017 12:24:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dS48i-0000wQ-QW for qemu-devel@nongnu.org; Mon, 03 Jul 2017 12:24:00 -0400 Received: from mout.kundenserver.de ([212.227.17.13]:58663) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dS48i-0000vJ-Fc for qemu-devel@nongnu.org; Mon, 03 Jul 2017 12:23:56 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue104 [212.227.15.183]) with ESMTPSA (Nemesis) id 0McEqN-1dBDRC48sp-00JZOU; Mon, 03 Jul 2017 18:23:34 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 3 Jul 2017 18:23:27 +0200 Message-Id: <20170703162328.24474-4-laurent@vivier.eu> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170703162328.24474-1-laurent@vivier.eu> References: <20170703162328.24474-1-laurent@vivier.eu> X-Provags-ID: V03:K0:DGpghOCXYuZGuSZa4zx90rzlds1/uEffAhJpMvFSYoBfld92g/u L+FjcTrE1BmAI5Hssvpw+t3NPzb9N+oKxm8sttcNfpy63LrFJNVaSVOwpCbOI9jS92p+A9d t3BgbUCJMTV8ajEH7Xgt2GR+WtUiGpBN7UZQ/jRny0fC5WUqnx4p0boeediEgNsqW6+N3pP ntOEE7Uw1SmcMGywVyjnA== X-UI-Out-Filterresults: notjunk:1;V01:K0:PgxCATZTdog=:c1OOJm1/j7sP73nJ/lAuWu DsHpXd9ZQmvD7X/IriZZWpcQ+Hq8VN6KHeQ/R61X8B7KTADdBRGlu3IRQWYxtEGNxeVeAawqp 2Np2ZfsKsl+mE9cWGPUBb6BY7P6/HcOxPfqweLYeYCzbUkkE0kKb/0oHlox+A5zjNLUlPpgmY SihhozKkxeTrc2S+gC0N38OgT7Pe490FJoWvQOyG1ddumMnP4C4UCDIcGR41Mb2QUorrt1d7Y GIlo+TtWEyxSKRdryXYJ7XgZdJlrlhyazGSPIa3DOzNOmwiunacBkh4j7E8973pfb3x7EoL5y YBYL40CAw7tGNvLNCS/9UIQdhL4NqyJ8zHZvSIaI1CcZMJQH0YovnqrnRGAYcmOX4Et5jYpbz eP1Rvl+nWh0rkL1VbBqEN5WuakiWijahQMXpC4cWBnDNDeWYL4cTTjjQajzueIyyp8+pkRqES kysPNKEpFAerZg3hIshsZvb7l4vFg2/M+Pyodl71oy0KFmxBT2LdcAs9otCzAFKZgfDzRjjB7 FgxUyRixAekqvDrGiuS6grKjvCf8iOwQYidXBuQVYt/d0RMVYW6FVRBtFhLSEyBu1w7mzzHby NQzkytAWa1M9xR+0ZWaX/Z8R8FP3dMFkj+gwk+F5vF1x0ZkNjZHFLVVrK0m25HjNbEsdLpSaD k0XrdJOzGI0ia9dnQDKs0wHleZsyQ8rRSKd/xMwe51xAUlzsPyTtr8z0jLcF8cyrSdIc= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.17.13 Subject: [Qemu-devel] [PATCH 3/4] target/m68k: add fmod/frem X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Use libm functions fmodl() and remainderl(). The quotient byte of the FPSR is updated with the result of the operation. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- target/m68k/cpu.h | 1 + target/m68k/fpu_helper.c | 35 +++++++++++++++++++++++++++++++++++ target/m68k/helper.h | 2 ++ target/m68k/translate.c | 6 ++++++ 4 files changed, 44 insertions(+) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index f8f4dd5..84794a9 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -236,6 +236,7 @@ typedef enum { /* Quotient */ =20 #define FPSR_QT_MASK 0x00ff0000 +#define FPSR_QT_SHIFT 16 =20 /* Floating-Point Control Register */ /* Rounding mode */ diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index 2b07cb9..715b9be 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -736,3 +736,38 @@ void HELPER(fsincos)(CPUM68KState *env, FPReg *res0, F= PReg *res1, FPReg *val) res1->d =3D ldouble_to_floatx80(dcos, &env->fp_status); res0->d =3D ldouble_to_floatx80(dsin, &env->fp_status); } + +static void make_quotient(CPUM68KState *env, long double val, uint32_t sig= n) +{ + uint32_t quotient =3D (uint32_t)fabsl(val); + quotient =3D (sign << 7) | (quotient & 0x7f); + env->fpsr =3D (env->fpsr & ~FPSR_QT_MASK) | (quotient << FPSR_QT_SHIFT= ); +} + +void HELPER(fmod)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) +{ + long double src, dst; + uint32_t sign =3D floatx80_is_neg(val0->d) ^ floatx80_is_neg(val1->d); + + src =3D floatx80_to_ldouble(val0->d); + dst =3D floatx80_to_ldouble(val1->d); + + dst =3D fmodl(dst, src); + + make_quotient(env, dst, sign); + res->d =3D ldouble_to_floatx80(dst, &env->fp_status); +} + +void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) +{ + long double src, dst; + uint32_t sign =3D floatx80_is_neg(val0->d) ^ floatx80_is_neg(val1->d); + + src =3D floatx80_to_ldouble(val0->d); + dst =3D floatx80_to_ldouble(val1->d); + + dst =3D remainderl(dst, src); + + make_quotient(env, dst, sign); + res->d =3D ldouble_to_floatx80(dst, &env->fp_status); +} diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 302b6c0..889978e 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -77,6 +77,8 @@ DEF_HELPER_3(fcosh, void, env, fp, fp) DEF_HELPER_3(facos, void, env, fp, fp) DEF_HELPER_3(fcos, void, env, fp, fp) DEF_HELPER_4(fsincos, void, env, fp, fp, fp) +DEF_HELPER_4(fmod, void, env, fp, fp, fp) +DEF_HELPER_4(frem, void, env, fp, fp, fp) =20 DEF_HELPER_3(mac_move, void, env, i32, i32) DEF_HELPER_3(macmulf, i64, env, i32, i32) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 8a712b3..fe9e0bf 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4727,6 +4727,9 @@ DISAS_INSN(fpu) case 0x64: /* fddiv */ gen_helper_fddiv(cpu_env, cpu_dest, cpu_src, cpu_dest); break; + case 0x21: /* fmod */ + gen_helper_fmod(cpu_env, cpu_dest, cpu_src, cpu_dest); + break; case 0x22: /* fadd */ gen_helper_fadd(cpu_env, cpu_dest, cpu_src, cpu_dest); break; @@ -4748,6 +4751,9 @@ DISAS_INSN(fpu) case 0x24: /* fsgldiv */ gen_helper_fsgldiv(cpu_env, cpu_dest, cpu_src, cpu_dest); break; + case 0x25: /* frem */ + gen_helper_frem(cpu_env, cpu_dest, cpu_src, cpu_dest); + break; case 0x27: /* fsglmul */ gen_helper_fsglmul(cpu_env, cpu_dest, cpu_src, cpu_dest); break; --=20 2.9.4 From nobody Wed May 8 01:59:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499099150452852.8938685161056; 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charset="utf-8" Signed-off-by: Laurent Vivier --- target/m68k/fpu_helper.c | 106 +++++++++++++++++++++++++++++++++++++++++++= ++++ target/m68k/helper.h | 3 ++ target/m68k/translate.c | 9 ++++ 3 files changed, 118 insertions(+) diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index 715b9be..88957fa 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -771,3 +771,109 @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPRe= g *val0, FPReg *val1) make_quotient(env, dst, sign); res->d =3D ldouble_to_floatx80(dst, &env->fp_status); } + +void HELPER(fgetexp)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + int32_t exp; + + if (floatx80_is_infinity(val->d)) { + res->d =3D floatx80_default_nan(NULL); + /* FIXME: set the OPERR bit int he FPSR */ + return; + } + if (floatx80_is_zero(val->d)) { + *res =3D *val; + return; + } + if (floatx80_is_zero_or_denormal(val->d)) { + res->d =3D int32_to_floatx80(-16384, &env->fp_status); + return; + } + + if (floatx80_is_any_nan(val->d)) { + res->d =3D floatx80_default_nan(NULL); + return; + } + + exp =3D (val->l.upper & 0x7fff) - 0x3fff; + + res->d =3D int32_to_floatx80(exp, &env->fp_status); +} + +void HELPER(fgetman)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + if (floatx80_is_infinity(val->d)) { + res->d =3D floatx80_default_nan(NULL); + /* FIXME: set the OPERR bit int he FPSR */ + return; + } + if (floatx80_is_zero(val->d) || + floatx80_is_any_nan(val->d)) { + *res =3D *val; + return; + } + + res->l.upper =3D (val->l.upper & 0x8000) | 0x3fff; + if (floatx80_is_zero_or_denormal(val->d)) { + res->l.lower =3D val->l.lower << 1; + } else { + res->l.lower =3D val->l.lower; + } +} + +void HELPER(fscale)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val= 1) +{ + int rounding_mode; + int32_t scale; + int32_t exp; + + if (floatx80_is_infinity(val0->d)) { + res->d =3D floatx80_default_nan(NULL); + /* FIXME: set the OPERR bit in the FPSR */ + return; + } + if (floatx80_is_any_nan(val0->d)) { + res->d =3D floatx80_default_nan(NULL); + return; + } + if (floatx80_is_infinity(val1->d) || + floatx80_is_zero_or_denormal(val1->d)) { + *res =3D *val1; + return; + } + if (floatx80_is_zero(val0->d)) { + res->d =3D floatx80_round(val1->d, &env->fp_status); + return; + } + + rounding_mode =3D get_float_rounding_mode(&env->fp_status); + set_float_rounding_mode(float_round_to_zero, &env->fp_status); + scale =3D floatx80_to_int32(val0->d, &env->fp_status); + set_float_rounding_mode(rounding_mode, &env->fp_status); + + if (scale >=3D 16384) { + if (floatx80_is_neg(val1->d)) { + res->d =3D floatx80_chs(floatx80_infinity); + } else { + res->d =3D floatx80_infinity; + } + /* FIXME: set OVFL in FPSR */ + return; + } + if (scale <=3D -16384) { + if (floatx80_is_neg(val1->d)) { + res->d =3D floatx80_chs(floatx80_zero); + } else { + res->d =3D floatx80_zero; + } + /* FIXME: set UNFL in FPSR */ + return; + } + + exp =3D (val1->l.upper & 0x7fff) + scale; + + res->l.upper =3D (val1->l.upper & 0x8000) | (exp & 0x7fff); + res->l.lower =3D val1->l.lower; + + res->d =3D floatx80_round(res->d, &env->fp_status); +} diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 889978e..a6be815 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -79,6 +79,9 @@ DEF_HELPER_3(fcos, void, env, fp, fp) DEF_HELPER_4(fsincos, void, env, fp, fp, fp) DEF_HELPER_4(fmod, void, env, fp, fp, fp) DEF_HELPER_4(frem, void, env, fp, fp, fp) +DEF_HELPER_3(fgetexp, void, env, fp, fp) +DEF_HELPER_3(fgetman, void, env, fp, fp) +DEF_HELPER_4(fscale, void, env, fp, fp, fp) =20 DEF_HELPER_3(mac_move, void, env, i32, i32) DEF_HELPER_3(macmulf, i64, env, i32, i32) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index fe9e0bf..348f4fb 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4718,6 +4718,12 @@ DISAS_INSN(fpu) case 0x1d: /* fcos */ gen_helper_fcos(cpu_env, cpu_dest, cpu_src); break; + case 0x1e: /* fgetexp */ + gen_helper_fgetexp(cpu_env, cpu_dest, cpu_src); + break; + case 0x1f: /* fgetman */ + gen_helper_fgetman(cpu_env, cpu_dest, cpu_src); + break; case 0x20: /* fdiv */ gen_helper_fdiv(cpu_env, cpu_dest, cpu_src, cpu_dest); break; @@ -4754,6 +4760,9 @@ DISAS_INSN(fpu) case 0x25: /* frem */ gen_helper_frem(cpu_env, cpu_dest, cpu_src, cpu_dest); break; + case 0x26: /* fscale */ + gen_helper_fscale(cpu_env, cpu_dest, cpu_src, cpu_dest); + break; case 0x27: /* fsglmul */ gen_helper_fsglmul(cpu_env, cpu_dest, cpu_src, cpu_dest); break; --=20 2.9.4