From nobody Mon May 6 03:06:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499027606701585.1276847476681; Sun, 2 Jul 2017 13:33:26 -0700 (PDT) Received: from localhost ([::1]:59171 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRlYb-0005FD-JE for importer@patchew.org; Sun, 02 Jul 2017 16:33:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59472) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRlTi-0001kf-CW for qemu-devel@nongnu.org; Sun, 02 Jul 2017 16:28:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dRlTh-0001H8-Ac for qemu-devel@nongnu.org; Sun, 02 Jul 2017 16:28:22 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:41568) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dRlTh-0001GL-4U for qemu-devel@nongnu.org; Sun, 02 Jul 2017 16:28:21 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1dRlTe-0003Gq-Pt; Sun, 02 Jul 2017 22:28:18 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1dRlTe-0007FH-4o; Sun, 02 Jul 2017 22:28:18 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sun, 2 Jul 2017 22:28:10 +0200 Message-Id: <20170702202814.27793-2-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170702202814.27793-1-aurelien@aurel32.net> References: <20170702202814.27793-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PATCH v2 1/5] target/sh4: do not check for PR bit for fabs instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bruno Haible , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The SH4 manual is not fully clear about that, but real hardware do not check for the PR bit, which allows to select between single or double precision, for the fabs instruction. This is probably what is meant by "Same operation is performed regardless of precision." Remove the check, and at the same time use a TCG instruction instead of a helper to clear one bit. LP: https://bugs.launchpad.net/qemu/+bug/1701821 Reported-by: Bruno Haible Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson --- target/sh4/helper.h | 2 -- target/sh4/op_helper.c | 10 ---------- target/sh4/translate.c | 15 +++------------ 3 files changed, 3 insertions(+), 24 deletions(-) diff --git a/target/sh4/helper.h b/target/sh4/helper.h index dce859caea..f715224822 100644 --- a/target/sh4/helper.h +++ b/target/sh4/helper.h @@ -16,8 +16,6 @@ DEF_HELPER_3(macw, void, env, i32, i32) =20 DEF_HELPER_2(ld_fpscr, void, env, i32) =20 -DEF_HELPER_FLAGS_1(fabs_FT, TCG_CALL_NO_RWG_SE, f32, f32) -DEF_HELPER_FLAGS_1(fabs_DT, TCG_CALL_NO_RWG_SE, f64, f64) DEF_HELPER_FLAGS_3(fadd_FT, TCG_CALL_NO_WG, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fadd_DT, TCG_CALL_NO_WG, f64, env, f64, f64) DEF_HELPER_FLAGS_2(fcnvsd_FT_DT, TCG_CALL_NO_WG, f64, env, f32) diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 528a40ac1d..5e3a3ba68c 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -252,16 +252,6 @@ static void update_fpscr(CPUSH4State *env, uintptr_t r= etaddr) } } =20 -float32 helper_fabs_FT(float32 t0) -{ - return float32_abs(t0); -} - -float64 helper_fabs_DT(float64 t0) -{ - return float64_abs(t0); -} - float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1) { set_float_exception_flags(0, &env->fp_status); diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 4f20537ef8..7c40945908 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1695,19 +1695,10 @@ static void _decode_opc(DisasContext * ctx) gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); } return; - case 0xf05d: /* fabs FRn/DRn */ + case 0xf05d: /* fabs FRn/DRn - FPCSR: Nothing */ CHECK_FPU_ENABLED - if (ctx->tbflags & FPSCR_PR) { - if (ctx->opcode & 0x0100) - break; /* illegal instruction */ - TCGv_i64 fp =3D tcg_temp_new_i64(); - gen_load_fpr64(fp, DREG(B11_8)); - gen_helper_fabs_DT(fp, fp); - gen_store_fpr64(fp, DREG(B11_8)); - tcg_temp_free_i64(fp); - } else { - gen_helper_fabs_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); - } + tcg_gen_andi_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], + 0x7fffffff); return; case 0xf06d: /* fsqrt FRn */ CHECK_FPU_ENABLED --=20 2.11.0 From nobody Mon May 6 03:06:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499027515792356.2132138287931; Sun, 2 Jul 2017 13:31:55 -0700 (PDT) Received: from localhost ([::1]:59167 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRlX8-0004LG-AT for importer@patchew.org; Sun, 02 Jul 2017 16:31:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59474) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRlTi-0001kg-D2 for qemu-devel@nongnu.org; Sun, 02 Jul 2017 16:28:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dRlTh-0001Gx-9w for qemu-devel@nongnu.org; Sun, 02 Jul 2017 16:28:22 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:41556) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dRlTh-0001GJ-4L for qemu-devel@nongnu.org; Sun, 02 Jul 2017 16:28:21 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1dRlTe-0003Gr-U8; Sun, 02 Jul 2017 22:28:19 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1dRlTe-0007FO-7W; Sun, 02 Jul 2017 22:28:18 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sun, 2 Jul 2017 22:28:11 +0200 Message-Id: <20170702202814.27793-3-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170702202814.27793-1-aurelien@aurel32.net> References: <20170702202814.27793-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PATCH v2 2/5] target/sh4: fix FPU unorderered compare X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bruno Haible , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In case of unordered compare, the fcmp instructions should either trigger and invalid exception (if enabled) or set T=3D0. The existing code left it unchanged. LP: https://bugs.launchpad.net/qemu/+bug/1701821 Reported-by: Bruno Haible Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson --- target/sh4/op_helper.c | 28 ++++++++-------------------- 1 file changed, 8 insertions(+), 20 deletions(-) diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 5e3a3ba68c..f228daf125 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -274,11 +274,8 @@ void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, f= loat32 t1) =20 set_float_exception_flags(0, &env->fp_status); relation =3D float32_compare(t0, t1, &env->fp_status); - if (unlikely(relation =3D=3D float_relation_unordered)) { - update_fpscr(env, GETPC()); - } else { - env->sr_t =3D (relation =3D=3D float_relation_equal); - } + update_fpscr(env, GETPC()); + env->sr_t =3D (relation =3D=3D float_relation_equal); } =20 void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1) @@ -287,11 +284,8 @@ void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, f= loat64 t1) =20 set_float_exception_flags(0, &env->fp_status); relation =3D float64_compare(t0, t1, &env->fp_status); - if (unlikely(relation =3D=3D float_relation_unordered)) { - update_fpscr(env, GETPC()); - } else { - env->sr_t =3D (relation =3D=3D float_relation_equal); - } + update_fpscr(env, GETPC()); + env->sr_t =3D (relation =3D=3D float_relation_equal); } =20 void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1) @@ -300,11 +294,8 @@ void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, f= loat32 t1) =20 set_float_exception_flags(0, &env->fp_status); relation =3D float32_compare(t0, t1, &env->fp_status); - if (unlikely(relation =3D=3D float_relation_unordered)) { - update_fpscr(env, GETPC()); - } else { - env->sr_t =3D (relation =3D=3D float_relation_greater); - } + update_fpscr(env, GETPC()); + env->sr_t =3D (relation =3D=3D float_relation_greater); } =20 void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1) @@ -313,11 +304,8 @@ void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, f= loat64 t1) =20 set_float_exception_flags(0, &env->fp_status); relation =3D float64_compare(t0, t1, &env->fp_status); - if (unlikely(relation =3D=3D float_relation_unordered)) { - update_fpscr(env, GETPC()); - } else { - env->sr_t =3D (relation =3D=3D float_relation_greater); - } + update_fpscr(env, GETPC()); + env->sr_t =3D (relation =3D=3D float_relation_greater); } =20 float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0) --=20 2.11.0 From nobody Mon May 6 03:06:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499027403191758.7785335255116; Sun, 2 Jul 2017 13:30:03 -0700 (PDT) Received: from localhost ([::1]:59156 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRlVJ-0002rg-9n for importer@patchew.org; Sun, 02 Jul 2017 16:30:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59466) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRlTi-0001kc-5K for qemu-devel@nongnu.org; Sun, 02 Jul 2017 16:28:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dRlTh-0001H2-Bm for qemu-devel@nongnu.org; Sun, 02 Jul 2017 16:28:22 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:41558) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dRlTh-0001GI-4X for qemu-devel@nongnu.org; Sun, 02 Jul 2017 16:28:21 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1dRlTf-0003Gs-0y; Sun, 02 Jul 2017 22:28:19 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1dRlTe-0007FV-AA; Sun, 02 Jul 2017 22:28:18 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sun, 2 Jul 2017 22:28:12 +0200 Message-Id: <20170702202814.27793-4-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170702202814.27793-1-aurelien@aurel32.net> References: <20170702202814.27793-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PATCH v2 3/5] target/sh4: fix FPSCR cause vs flag inversion X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bruno Haible , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The floating-point status/control register contains cause and flag bits. The cause bits are set to 0 before executing the instruction, while the flag bits hold the status of the exception generated after the field was last cleared. Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson --- target/sh4/op_helper.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index f228daf125..f2e39c5ca6 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -219,29 +219,29 @@ static void update_fpscr(CPUSH4State *env, uintptr_t = retaddr) =20 xcpt =3D get_float_exception_flags(&env->fp_status); =20 - /* Clear the flag entries */ - env->fpscr &=3D ~FPSCR_FLAG_MASK; + /* Clear the cause entries */ + env->fpscr &=3D ~FPSCR_CAUSE_MASK; =20 if (unlikely(xcpt)) { if (xcpt & float_flag_invalid) { - env->fpscr |=3D FPSCR_FLAG_V; + env->fpscr |=3D FPSCR_CAUSE_V; } if (xcpt & float_flag_divbyzero) { - env->fpscr |=3D FPSCR_FLAG_Z; + env->fpscr |=3D FPSCR_CAUSE_Z; } if (xcpt & float_flag_overflow) { - env->fpscr |=3D FPSCR_FLAG_O; + env->fpscr |=3D FPSCR_CAUSE_O; } if (xcpt & float_flag_underflow) { - env->fpscr |=3D FPSCR_FLAG_U; + env->fpscr |=3D FPSCR_CAUSE_U; } if (xcpt & float_flag_inexact) { - env->fpscr |=3D FPSCR_FLAG_I; + env->fpscr |=3D FPSCR_CAUSE_I; } =20 - /* Accumulate in cause entries */ - env->fpscr |=3D (env->fpscr & FPSCR_FLAG_MASK) - << (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT); + /* Accumulate in flag entries */ + env->fpscr |=3D (env->fpscr & FPSCR_CAUSE_MASK) + >> (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT); =20 /* Generate an exception if enabled */ cause =3D (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT; --=20 2.11.0 From nobody Mon May 6 03:06:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499027403128980.9732910853187; Sun, 2 Jul 2017 13:30:03 -0700 (PDT) Received: from localhost ([::1]:59157 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRlVI-0002rt-R8 for importer@patchew.org; Sun, 02 Jul 2017 16:30:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59463) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRlTi-0001kb-4a for qemu-devel@nongnu.org; Sun, 02 Jul 2017 16:28:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dRlTh-0001H4-BR for qemu-devel@nongnu.org; Sun, 02 Jul 2017 16:28:22 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:41570) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dRlTh-0001GM-4F for qemu-devel@nongnu.org; Sun, 02 Jul 2017 16:28:21 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1dRlTf-0003Gv-5U; Sun, 02 Jul 2017 22:28:19 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1dRlTe-0007Fc-DE; Sun, 02 Jul 2017 22:28:18 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sun, 2 Jul 2017 22:28:13 +0200 Message-Id: <20170702202814.27793-5-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170702202814.27793-1-aurelien@aurel32.net> References: <20170702202814.27793-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PATCH v2 4/5] target/sh4: do not use a helper to implement fneg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bruno Haible , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There is no need to use a helper to flip one bit, just use a TCG xor instruction instead. Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson --- target/sh4/helper.h | 1 - target/sh4/op_helper.c | 5 ----- target/sh4/translate.c | 5 ++--- 3 files changed, 2 insertions(+), 9 deletions(-) diff --git a/target/sh4/helper.h b/target/sh4/helper.h index f715224822..d2398922dd 100644 --- a/target/sh4/helper.h +++ b/target/sh4/helper.h @@ -32,7 +32,6 @@ DEF_HELPER_FLAGS_2(float_DT, TCG_CALL_NO_WG, f64, env, i3= 2) DEF_HELPER_FLAGS_4(fmac_FT, TCG_CALL_NO_WG, f32, env, f32, f32, f32) DEF_HELPER_FLAGS_3(fmul_FT, TCG_CALL_NO_WG, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fmul_DT, TCG_CALL_NO_WG, f64, env, f64, f64) -DEF_HELPER_FLAGS_1(fneg_T, TCG_CALL_NO_RWG_SE, f32, f32) DEF_HELPER_FLAGS_3(fsub_FT, TCG_CALL_NO_WG, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fsub_DT, TCG_CALL_NO_WG, f64, env, f64, f64) DEF_HELPER_FLAGS_2(fsqrt_FT, TCG_CALL_NO_WG, f32, env, f32) diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index f2e39c5ca6..64206cf803 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -384,11 +384,6 @@ float64 helper_fmul_DT(CPUSH4State *env, float64 t0, f= loat64 t1) return t0; } =20 -float32 helper_fneg_T(float32 t0) -{ - return float32_chs(t0); -} - float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0) { set_float_exception_flags(0, &env->fp_status); diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 7c40945908..8098228c51 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1691,9 +1691,8 @@ static void _decode_opc(DisasContext * ctx) return; case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ CHECK_FPU_ENABLED - { - gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); - } + tcg_gen_xori_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], + 0x80000000); return; case 0xf05d: /* fabs FRn/DRn - FPCSR: Nothing */ CHECK_FPU_ENABLED --=20 2.11.0 From nobody Mon May 6 03:06:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499027516197950.6573588862525; Sun, 2 Jul 2017 13:31:56 -0700 (PDT) Received: from localhost ([::1]:59168 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRlX8-0004M4-Vs for importer@patchew.org; Sun, 02 Jul 2017 16:31:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59470) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRlTi-0001ke-AR for qemu-devel@nongnu.org; Sun, 02 Jul 2017 16:28:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dRlTh-0001HF-Av for qemu-devel@nongnu.org; Sun, 02 Jul 2017 16:28:22 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:41554) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dRlTh-0001GK-4B for qemu-devel@nongnu.org; Sun, 02 Jul 2017 16:28:21 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1dRlTf-0003Gw-83; Sun, 02 Jul 2017 22:28:19 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1dRlTe-0007Fj-GQ; Sun, 02 Jul 2017 22:28:18 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sun, 2 Jul 2017 22:28:14 +0200 Message-Id: <20170702202814.27793-6-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170702202814.27793-1-aurelien@aurel32.net> References: <20170702202814.27793-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PATCH v2 5/5] target/sh4: return result of fcmp using TCG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bruno Haible , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since that the T bit of the SR register is mapped using a TGC global, it's better to return the value through TCG than writing it directly. It allows to declare the helpers with the flag TCG_CALL_NO_WG. Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson --- target/sh4/helper.h | 8 ++++---- target/sh4/op_helper.c | 16 ++++++++-------- target/sh4/translate.c | 10 ++++++---- 3 files changed, 18 insertions(+), 16 deletions(-) diff --git a/target/sh4/helper.h b/target/sh4/helper.h index d2398922dd..767a6d5209 100644 --- a/target/sh4/helper.h +++ b/target/sh4/helper.h @@ -21,10 +21,10 @@ DEF_HELPER_FLAGS_3(fadd_DT, TCG_CALL_NO_WG, f64, env, f= 64, f64) DEF_HELPER_FLAGS_2(fcnvsd_FT_DT, TCG_CALL_NO_WG, f64, env, f32) DEF_HELPER_FLAGS_2(fcnvds_DT_FT, TCG_CALL_NO_WG, f32, env, f64) =20 -DEF_HELPER_3(fcmp_eq_FT, void, env, f32, f32) -DEF_HELPER_3(fcmp_eq_DT, void, env, f64, f64) -DEF_HELPER_3(fcmp_gt_FT, void, env, f32, f32) -DEF_HELPER_3(fcmp_gt_DT, void, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmp_eq_FT, TCG_CALL_NO_WG, i32, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmp_eq_DT, TCG_CALL_NO_WG, i32, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmp_gt_FT, TCG_CALL_NO_WG, i32, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmp_gt_DT, TCG_CALL_NO_WG, i32, env, f64, f64) DEF_HELPER_FLAGS_3(fdiv_FT, TCG_CALL_NO_WG, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fdiv_DT, TCG_CALL_NO_WG, f64, env, f64, f64) DEF_HELPER_FLAGS_2(float_FT, TCG_CALL_NO_WG, f32, env, i32) diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 64206cf803..c3d19b1f61 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -268,44 +268,44 @@ float64 helper_fadd_DT(CPUSH4State *env, float64 t0, = float64 t1) return t0; } =20 -void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1) +uint32_t helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1) { int relation; =20 set_float_exception_flags(0, &env->fp_status); relation =3D float32_compare(t0, t1, &env->fp_status); update_fpscr(env, GETPC()); - env->sr_t =3D (relation =3D=3D float_relation_equal); + return relation =3D=3D float_relation_equal; } =20 -void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1) +uint32_t helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1) { int relation; =20 set_float_exception_flags(0, &env->fp_status); relation =3D float64_compare(t0, t1, &env->fp_status); update_fpscr(env, GETPC()); - env->sr_t =3D (relation =3D=3D float_relation_equal); + return relation =3D=3D float_relation_equal; } =20 -void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1) +uint32_t helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1) { int relation; =20 set_float_exception_flags(0, &env->fp_status); relation =3D float32_compare(t0, t1, &env->fp_status); update_fpscr(env, GETPC()); - env->sr_t =3D (relation =3D=3D float_relation_greater); + return relation =3D=3D float_relation_greater; } =20 -void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1) +uint32_t helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1) { int relation; =20 set_float_exception_flags(0, &env->fp_status); relation =3D float64_compare(t0, t1, &env->fp_status); update_fpscr(env, GETPC()); - env->sr_t =3D (relation =3D=3D float_relation_greater); + return relation =3D=3D float_relation_greater; } =20 float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 8098228c51..87b04f0d39 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1077,10 +1077,10 @@ static void _decode_opc(DisasContext * ctx) gen_helper_fdiv_DT(fp0, cpu_env, fp0, fp1); break; case 0xf004: /* fcmp/eq Rm,Rn */ - gen_helper_fcmp_eq_DT(cpu_env, fp0, fp1); + gen_helper_fcmp_eq_DT(cpu_sr_t, cpu_env, fp0, fp1); return; case 0xf005: /* fcmp/gt Rm,Rn */ - gen_helper_fcmp_gt_DT(cpu_env, fp0, fp1); + gen_helper_fcmp_gt_DT(cpu_sr_t, cpu_env, fp0, fp1); return; } gen_store_fpr64(fp0, DREG(B11_8)); @@ -1109,11 +1109,13 @@ static void _decode_opc(DisasContext * ctx) cpu_fregs[FREG(B7_4)]); break; case 0xf004: /* fcmp/eq Rm,Rn */ - gen_helper_fcmp_eq_FT(cpu_env, cpu_fregs[FREG(B11_8)], + gen_helper_fcmp_eq_FT(cpu_sr_t, cpu_env, + cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); return; case 0xf005: /* fcmp/gt Rm,Rn */ - gen_helper_fcmp_gt_FT(cpu_env, cpu_fregs[FREG(B11_8)], + gen_helper_fcmp_gt_FT(cpu_sr_t, cpu_env, + cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); return; } --=20 2.11.0