From nobody Fri May 3 02:40:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499013277173445.07505258677065; Sun, 2 Jul 2017 09:34:37 -0700 (PDT) Received: from localhost ([::1]:58604 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRhpT-00013l-VP for importer@patchew.org; Sun, 02 Jul 2017 12:34:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53540) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRhnU-0007mE-FW for qemu-devel@nongnu.org; Sun, 02 Jul 2017 12:32:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dRhnT-0006kA-63 for qemu-devel@nongnu.org; Sun, 02 Jul 2017 12:32:32 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:40224) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dRhnT-0006hp-0P for qemu-devel@nongnu.org; Sun, 02 Jul 2017 12:32:31 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1dRhnP-0003E4-Rn; Sun, 02 Jul 2017 18:32:27 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1dRhnN-00026y-AC; Sun, 02 Jul 2017 18:32:25 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sun, 2 Jul 2017 18:32:19 +0200 Message-Id: <20170702163220.8039-2-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170702163220.8039-1-aurelien@aurel32.net> References: <20170702163220.8039-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PATCH 1/2] target/sh4: do not check for PR bit for fabs instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bruno Haible , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The SH4 manual is not fully clear about that, but real hardware do not check for the PR bit, which allows to select between single or double precision, for the fabs instruction. This is probably what is meant by "Same operation is performed regardless of precision." Remove the check, and at the same time use a TCG instruction instead of a helper to clear one bit. LP: https://bugs.launchpad.net/qemu/+bug/1701821 Reported-by: Bruno Haible Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson --- target/sh4/helper.h | 2 -- target/sh4/op_helper.c | 10 ---------- target/sh4/translate.c | 15 +++------------ 3 files changed, 3 insertions(+), 24 deletions(-) diff --git a/target/sh4/helper.h b/target/sh4/helper.h index dce859caea..f715224822 100644 --- a/target/sh4/helper.h +++ b/target/sh4/helper.h @@ -16,8 +16,6 @@ DEF_HELPER_3(macw, void, env, i32, i32) =20 DEF_HELPER_2(ld_fpscr, void, env, i32) =20 -DEF_HELPER_FLAGS_1(fabs_FT, TCG_CALL_NO_RWG_SE, f32, f32) -DEF_HELPER_FLAGS_1(fabs_DT, TCG_CALL_NO_RWG_SE, f64, f64) DEF_HELPER_FLAGS_3(fadd_FT, TCG_CALL_NO_WG, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fadd_DT, TCG_CALL_NO_WG, f64, env, f64, f64) DEF_HELPER_FLAGS_2(fcnvsd_FT_DT, TCG_CALL_NO_WG, f64, env, f32) diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 528a40ac1d..5e3a3ba68c 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -252,16 +252,6 @@ static void update_fpscr(CPUSH4State *env, uintptr_t r= etaddr) } } =20 -float32 helper_fabs_FT(float32 t0) -{ - return float32_abs(t0); -} - -float64 helper_fabs_DT(float64 t0) -{ - return float64_abs(t0); -} - float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1) { set_float_exception_flags(0, &env->fp_status); diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 4f20537ef8..7c40945908 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1695,19 +1695,10 @@ static void _decode_opc(DisasContext * ctx) gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); } return; - case 0xf05d: /* fabs FRn/DRn */ + case 0xf05d: /* fabs FRn/DRn - FPCSR: Nothing */ CHECK_FPU_ENABLED - if (ctx->tbflags & FPSCR_PR) { - if (ctx->opcode & 0x0100) - break; /* illegal instruction */ - TCGv_i64 fp =3D tcg_temp_new_i64(); - gen_load_fpr64(fp, DREG(B11_8)); - gen_helper_fabs_DT(fp, fp); - gen_store_fpr64(fp, DREG(B11_8)); - tcg_temp_free_i64(fp); - } else { - gen_helper_fabs_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); - } + tcg_gen_andi_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], + 0x7fffffff); return; case 0xf06d: /* fsqrt FRn */ CHECK_FPU_ENABLED --=20 2.11.0 From nobody Fri May 3 02:40:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499013269578536.9962828126456; Sun, 2 Jul 2017 09:34:29 -0700 (PDT) Received: from localhost ([::1]:58603 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRhpL-0000zc-LV for importer@patchew.org; Sun, 02 Jul 2017 12:34:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53533) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRhnU-0007mD-1k for qemu-devel@nongnu.org; Sun, 02 Jul 2017 12:32:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dRhnT-0006kM-6r for qemu-devel@nongnu.org; Sun, 02 Jul 2017 12:32:32 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:40220) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dRhnT-0006hn-0X for qemu-devel@nongnu.org; Sun, 02 Jul 2017 12:32:31 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1dRhnP-0003E5-Pn; Sun, 02 Jul 2017 18:32:27 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1dRhnN-000275-DM; Sun, 02 Jul 2017 18:32:25 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sun, 2 Jul 2017 18:32:20 +0200 Message-Id: <20170702163220.8039-3-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170702163220.8039-1-aurelien@aurel32.net> References: <20170702163220.8039-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PATCH 2/2] target/sh4: do not use a helper to implement fneg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bruno Haible , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There is no need to use a helper to flip one bit, just use a TCG xor instruction instead. Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson --- target/sh4/helper.h | 1 - target/sh4/op_helper.c | 5 ----- target/sh4/translate.c | 5 ++--- 3 files changed, 2 insertions(+), 9 deletions(-) diff --git a/target/sh4/helper.h b/target/sh4/helper.h index f715224822..d2398922dd 100644 --- a/target/sh4/helper.h +++ b/target/sh4/helper.h @@ -32,7 +32,6 @@ DEF_HELPER_FLAGS_2(float_DT, TCG_CALL_NO_WG, f64, env, i3= 2) DEF_HELPER_FLAGS_4(fmac_FT, TCG_CALL_NO_WG, f32, env, f32, f32, f32) DEF_HELPER_FLAGS_3(fmul_FT, TCG_CALL_NO_WG, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fmul_DT, TCG_CALL_NO_WG, f64, env, f64, f64) -DEF_HELPER_FLAGS_1(fneg_T, TCG_CALL_NO_RWG_SE, f32, f32) DEF_HELPER_FLAGS_3(fsub_FT, TCG_CALL_NO_WG, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fsub_DT, TCG_CALL_NO_WG, f64, env, f64, f64) DEF_HELPER_FLAGS_2(fsqrt_FT, TCG_CALL_NO_WG, f32, env, f32) diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 5e3a3ba68c..d561141301 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -396,11 +396,6 @@ float64 helper_fmul_DT(CPUSH4State *env, float64 t0, f= loat64 t1) return t0; } =20 -float32 helper_fneg_T(float32 t0) -{ - return float32_chs(t0); -} - float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0) { set_float_exception_flags(0, &env->fp_status); diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 7c40945908..8098228c51 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1691,9 +1691,8 @@ static void _decode_opc(DisasContext * ctx) return; case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ CHECK_FPU_ENABLED - { - gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); - } + tcg_gen_xori_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], + 0x80000000); return; case 0xf05d: /* fabs FRn/DRn - FPCSR: Nothing */ CHECK_FPU_ENABLED --=20 2.11.0