From nobody Sat Apr 27 15:53:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498825965638817.2331025552952; Fri, 30 Jun 2017 05:32:45 -0700 (PDT) Received: from localhost ([::1]:44339 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQv6I-0000cY-Vu for importer@patchew.org; Fri, 30 Jun 2017 08:32:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33276) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQv4f-00086P-Oq for qemu-devel@nongnu.org; Fri, 30 Jun 2017 08:31:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQv4b-0005vv-95 for qemu-devel@nongnu.org; Fri, 30 Jun 2017 08:31:01 -0400 Received: from mout.kundenserver.de ([212.227.126.130]:50272) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dQv4a-0005qi-UH for qemu-devel@nongnu.org; Fri, 30 Jun 2017 08:30:57 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue001 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MGb9E-1dVN2S2bmC-00DJ8L; Fri, 30 Jun 2017 14:30:52 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Fri, 30 Jun 2017 14:30:44 +0200 Message-Id: <20170630123050.19834-2-laurent@vivier.eu> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170630123050.19834-1-laurent@vivier.eu> References: <20170630123050.19834-1-laurent@vivier.eu> X-Provags-ID: V03:K0:xXk3Y+TzcK9ohfTdjuNhBicW9BHNomaqPkezaaeDOUsEOmj76Sl oUuwSgz61R4wQw4pDHz3m5j3n3XzonAZjE8f8foPuVXdXN8UeNlzXoLchTIY8YNwp0uc8k0 0Q1iT2Nn5+/O7hszLXVMdCedVBmMoF+YmQ95JBG/D3PcT8zUVKRI4IJZXeacE5N5Db5c3ej pEjh8Z4DvDb4JOS1w5cug== X-UI-Out-Filterresults: notjunk:1;V01:K0:hLKTBTTy4Iw=:HDGymQBM2ixBSorX+KeDiR f6L74U6U4neZAR2fZdfa5JcfO4z/ggh9xYFJWnVM9i3IvkXg/TQQyZg9GbyHuERCSO0N1uUBv G+A48geB/V0DjEHzn21Yob8KvQFikHET2sZM+U9RT/C6sO69EZ9QVtV9CITM06G2Q6seK7kBI R/Kwr+xi8+CtZzDtILSyUJODpDwbQtYK9qCSV1cm8sMhWVnrC0hrBpLNtcBSG0SnjMD4SdfL+ IUzBug8qMmjUhFMnDbf/YMxTPtTHr8aD4cwBScBD7mGfNAlYbHQFN8+BDvBBOJpUCv9DTxnXW ri6/PKTKficXNhkeOh2kVYxXnLwHN2RhtoZNyn+uF5fJ/Ab3B4ugVUVC7eycyrhTABpR9Udut gm/htCtjOgpFHvS8a62F33dUSAWEM0YqUkkM8tNp2rqkyx5vz7r2sLLTM0eyWCq2kXxuoQBtW lc4uks0TLAn+yX7P2Agl36IPFfgR8ul9unhwFx/KxbPv37/8lD/AKaVOyrE/W4IvAWwXzmLCO 7P4L7Aqa/wMWdVAbierbi+IQNW79L6wZwrMYEvHpj0jn5gfwKFIUoBB6732L05Qmyk8Hvr5yt W1z9FphxlzCqhc0+TzRkXMynxwc6dV725UQv/F3o3FZfYPz+ieN0aPBCSQj6vjKkHgA461WF/ di/eOWpH3NXJdUmer9cLswUYP8+MFolJfqYgRDhuwL0HAi2VrXdzUaxPWoRYsH4bW6Ts= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.130 Subject: [Qemu-devel] [PULL 1/7] target/m68k: add fscc. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" use DisasCompare with FPU conditions in fscc and fbcc. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20170628204241.32106-2-laurent@vivier.eu> --- target/m68k/translate.c | 210 ++++++++++++++++++++++++++++++--------------= ---- 1 file changed, 131 insertions(+), 79 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 7aa0fdc..5f4bedc 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4633,142 +4633,193 @@ undef: disas_undef_fpu(env, s, insn); } =20 -DISAS_INSN(fbcc) +static void gen_fcc_cond(DisasCompare *c, DisasContext *s, int cond) { - uint32_t offset; - uint32_t addr; - TCGLabel *l1; - TCGv tmp, fpsr; - - addr =3D s->pc; - offset =3D cpu_ldsw_code(env, s->pc); - s->pc +=3D 2; - if (insn & (1 << 6)) { - offset =3D (offset << 16) | read_im16(env, s); - } + TCGv fpsr; =20 + c->g1 =3D 1; + c->v2 =3D tcg_const_i32(0); + c->g2 =3D 0; + /* TODO: Raise BSUN exception. */ fpsr =3D tcg_temp_new(); gen_load_fcr(s, fpsr, M68K_FPSR); - l1 =3D gen_new_label(); - /* TODO: Raise BSUN exception. */ - /* Jump to l1 if condition is true. */ - switch (insn & 0x3f) { + switch (cond) { case 0: /* False */ case 16: /* Signaling False */ + c->v1 =3D c->v2; + c->tcond =3D TCG_COND_NEVER; break; case 1: /* EQual Z */ case 17: /* Signaling EQual Z */ - tmp =3D tcg_temp_new(); - tcg_gen_andi_i32(tmp, fpsr, FPSR_CC_Z); - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); + c->v1 =3D tcg_temp_new(); + c->g1 =3D 0; + tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z); + c->tcond =3D TCG_COND_NE; break; case 2: /* Ordered Greater Than !(A || Z || N) */ case 18: /* Greater Than !(A || Z || N) */ - tmp =3D tcg_temp_new(); - tcg_gen_andi_i32(tmp, fpsr, + c->v1 =3D tcg_temp_new(); + c->g1 =3D 0; + tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N); - tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); + c->tcond =3D TCG_COND_EQ; break; case 3: /* Ordered Greater than or Equal Z || !(A || N) */ case 19: /* Greater than or Equal Z || !(A || N) */ - assert(FPSR_CC_A =3D=3D (FPSR_CC_N >> 3)); - tmp =3D tcg_temp_new(); - tcg_gen_shli_i32(tmp, fpsr, 3); - tcg_gen_or_i32(tmp, tmp, fpsr); - tcg_gen_xori_i32(tmp, tmp, FPSR_CC_N); - tcg_gen_andi_i32(tmp, tmp, FPSR_CC_N | FPSR_CC_Z); - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); + c->v1 =3D tcg_temp_new(); + c->g1 =3D 0; + tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A); + tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A)= ); + tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_Z | FPSR_CC_N); + tcg_gen_or_i32(c->v1, c->v1, fpsr); + tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N); + c->tcond =3D TCG_COND_NE; break; case 4: /* Ordered Less Than !(!N || A || Z); */ case 20: /* Less Than !(!N || A || Z); */ - tmp =3D tcg_temp_new(); - tcg_gen_xori_i32(tmp, fpsr, FPSR_CC_N); - tcg_gen_andi_i32(tmp, tmp, FPSR_CC_N | FPSR_CC_A | FPSR_CC_Z); - tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); + c->v1 =3D tcg_temp_new(); + c->g1 =3D 0; + tcg_gen_xori_i32(c->v1, fpsr, FPSR_CC_N); + tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_N | FPSR_CC_A | FPSR_CC_Z); + c->tcond =3D TCG_COND_EQ; break; case 5: /* Ordered Less than or Equal Z || (N && !A) */ case 21: /* Less than or Equal Z || (N && !A) */ - assert(FPSR_CC_A =3D=3D (FPSR_CC_N >> 3)); - tmp =3D tcg_temp_new(); - tcg_gen_xori_i32(tmp, fpsr, FPSR_CC_A); - tcg_gen_shli_i32(tmp, tmp, 3); - tcg_gen_ori_i32(tmp, tmp, FPSR_CC_Z); - tcg_gen_and_i32(tmp, tmp, fpsr); - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); + c->v1 =3D tcg_temp_new(); + c->g1 =3D 0; + tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A); + tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A)= ); + tcg_gen_andc_i32(c->v1, fpsr, c->v1); + tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_Z | FPSR_CC_N); + c->tcond =3D TCG_COND_NE; break; case 6: /* Ordered Greater or Less than !(A || Z) */ case 22: /* Greater or Less than !(A || Z) */ - tmp =3D tcg_temp_new(); - tcg_gen_andi_i32(tmp, fpsr, FPSR_CC_A | FPSR_CC_Z); - tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); + c->v1 =3D tcg_temp_new(); + c->g1 =3D 0; + tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z); + c->tcond =3D TCG_COND_EQ; break; case 7: /* Ordered !A */ case 23: /* Greater, Less or Equal !A */ - tmp =3D tcg_temp_new(); - tcg_gen_andi_i32(tmp, fpsr, FPSR_CC_A); - tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); + c->v1 =3D tcg_temp_new(); + c->g1 =3D 0; + tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A); + c->tcond =3D TCG_COND_EQ; break; case 8: /* Unordered A */ case 24: /* Not Greater, Less or Equal A */ - tmp =3D tcg_temp_new(); - tcg_gen_andi_i32(tmp, fpsr, FPSR_CC_A); - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); + c->v1 =3D tcg_temp_new(); + c->g1 =3D 0; + tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A); + c->tcond =3D TCG_COND_NE; break; case 9: /* Unordered or Equal A || Z */ case 25: /* Not Greater or Less then A || Z */ - tmp =3D tcg_temp_new(); - tcg_gen_andi_i32(tmp, fpsr, FPSR_CC_A | FPSR_CC_Z); - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); + c->v1 =3D tcg_temp_new(); + c->g1 =3D 0; + tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z); + c->tcond =3D TCG_COND_NE; break; case 10: /* Unordered or Greater Than A || !(N || Z)) */ case 26: /* Not Less or Equal A || !(N || Z)) */ - assert(FPSR_CC_Z =3D=3D (FPSR_CC_N >> 1)); - tmp =3D tcg_temp_new(); - tcg_gen_shli_i32(tmp, fpsr, 1); - tcg_gen_or_i32(tmp, tmp, fpsr); - tcg_gen_xori_i32(tmp, tmp, FPSR_CC_N); - tcg_gen_andi_i32(tmp, tmp, FPSR_CC_N | FPSR_CC_A); - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); + c->v1 =3D tcg_temp_new(); + c->g1 =3D 0; + tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z); + tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z)= ); + tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_A | FPSR_CC_N); + tcg_gen_or_i32(c->v1, c->v1, fpsr); + tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N); + c->tcond =3D TCG_COND_NE; break; case 11: /* Unordered or Greater or Equal A || Z || !N */ case 27: /* Not Less Than A || Z || !N */ - tmp =3D tcg_temp_new(); - tcg_gen_andi_i32(tmp, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N); - tcg_gen_xori_i32(tmp, tmp, FPSR_CC_N); - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); + c->v1 =3D tcg_temp_new(); + c->g1 =3D 0; + tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N); + tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N); + c->tcond =3D TCG_COND_NE; break; case 12: /* Unordered or Less Than A || (N && !Z) */ case 28: /* Not Greater than or Equal A || (N && !Z) */ - assert(FPSR_CC_Z =3D=3D (FPSR_CC_N >> 1)); - tmp =3D tcg_temp_new(); - tcg_gen_xori_i32(tmp, fpsr, FPSR_CC_Z); - tcg_gen_shli_i32(tmp, tmp, 1); - tcg_gen_ori_i32(tmp, tmp, FPSR_CC_A); - tcg_gen_and_i32(tmp, tmp, fpsr); - tcg_gen_andi_i32(tmp, tmp, FPSR_CC_A | FPSR_CC_N); - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); + c->v1 =3D tcg_temp_new(); + c->g1 =3D 0; + tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z); + tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z)= ); + tcg_gen_andc_i32(c->v1, fpsr, c->v1); + tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_A | FPSR_CC_N); + c->tcond =3D TCG_COND_NE; break; case 13: /* Unordered or Less or Equal A || Z || N */ case 29: /* Not Greater Than A || Z || N */ - tmp =3D tcg_temp_new(); - tcg_gen_andi_i32(tmp, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N); - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); + c->v1 =3D tcg_temp_new(); + c->g1 =3D 0; + tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N); + c->tcond =3D TCG_COND_NE; break; case 14: /* Not Equal !Z */ case 30: /* Signaling Not Equal !Z */ - tmp =3D tcg_temp_new(); - tcg_gen_andi_i32(tmp, fpsr, FPSR_CC_Z); - tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); + c->v1 =3D tcg_temp_new(); + c->g1 =3D 0; + tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z); + c->tcond =3D TCG_COND_EQ; break; case 15: /* True */ case 31: /* Signaling True */ - tcg_gen_br(l1); + c->v1 =3D c->v2; + c->tcond =3D TCG_COND_ALWAYS; break; } tcg_temp_free(fpsr); +} + +static void gen_fjmpcc(DisasContext *s, int cond, TCGLabel *l1) +{ + DisasCompare c; + + gen_fcc_cond(&c, s, cond); + tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1); + free_cond(&c); +} + +DISAS_INSN(fbcc) +{ + uint32_t offset; + uint32_t base; + TCGLabel *l1; + + base =3D s->pc; + offset =3D (int16_t)read_im16(env, s); + if (insn & (1 << 6)) { + offset =3D (offset << 16) | read_im16(env, s); + } + + l1 =3D gen_new_label(); + update_cc_op(s); + gen_fjmpcc(s, insn & 0x3f, l1); gen_jmp_tb(s, 0, s->pc); gen_set_label(l1); - gen_jmp_tb(s, 1, addr + offset); + gen_jmp_tb(s, 1, base + offset); +} + +DISAS_INSN(fscc) +{ + DisasCompare c; + int cond; + TCGv tmp; + uint16_t ext; + + ext =3D read_im16(env, s); + cond =3D ext & 0x3f; + gen_fcc_cond(&c, s, cond); + + tmp =3D tcg_temp_new(); + tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2); + free_cond(&c); + + tcg_gen_neg_i32(tmp, tmp); + DEST_EA(env, insn, OS_BYTE, tmp, NULL); + tcg_temp_free(tmp); } =20 DISAS_INSN(frestore) @@ -5349,6 +5400,7 @@ void register_m68k_insns (CPUM68KState *env) INSN(frestore, f340, ffc0, CF_FPU); INSN(fsave, f300, ffc0, CF_FPU); INSN(fpu, f200, ffc0, FPU); + INSN(fscc, f240, ffc0, FPU); INSN(fbcc, f280, ff80, FPU); INSN(frestore, f340, ffc0, FPU); INSN(fsave, f300, ffc0, FPU); --=20 2.9.4 From nobody Sat Apr 27 15:53:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149882623019576.00922834885932; Fri, 30 Jun 2017 05:37:10 -0700 (PDT) Received: from localhost ([::1]:44360 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQvAZ-0004eS-Qn for importer@patchew.org; Fri, 30 Jun 2017 08:37:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33317) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQv4n-0008Hc-Qy for qemu-devel@nongnu.org; Fri, 30 Jun 2017 08:31:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQv4a-0005tv-HD for qemu-devel@nongnu.org; Fri, 30 Jun 2017 08:31:09 -0400 Received: from mout.kundenserver.de ([212.227.126.134]:58723) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dQv4a-0005rO-5w for qemu-devel@nongnu.org; Fri, 30 Jun 2017 08:30:56 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue001 [212.227.15.167]) with ESMTPSA (Nemesis) id 0LtAB1-1dtMF40aYV-012p9u; Fri, 30 Jun 2017 14:30:53 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Fri, 30 Jun 2017 14:30:45 +0200 Message-Id: <20170630123050.19834-3-laurent@vivier.eu> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170630123050.19834-1-laurent@vivier.eu> References: <20170630123050.19834-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K0:ANz5nTVk4okz4ioBJbzEO5da94KXBcpHmBpbVuj2iWzTZqlRYqR HEHlu+/pDJVeHKPSFJBeXOLBZrDmMPSt8yoCq+iuAK+b47YaB90L1qZxrNQkD7vvoX3mps1 +Hsw36IjlgHimPnSgdJ0ymCtTNvNTkg4gHqN9KF7LfLtR8UCLHZKTJ/fS4AbnY1EY+xrcQE bvfpwuMEmQR2ytL2jtZeA== X-UI-Out-Filterresults: notjunk:1;V01:K0:wP0j1vAE8KU=:LKD3kSgdhjLcOwAWBO63QV zSdCakzJXGu+oSpAKqJvnRziSy/JtY8GKZuBW9j9wUUFkhjQHv7WaE9CfBy7QS35SzVp4sd/N DwXqtKMMqvzUMFU3QTqDWnBnrvRY2qkWRrCLNYhnyODdbetml3jGGRsBs+EBsp/uI0aV0HE5o LePMz6oz+gcgKXMLefIYqA6Vv+wFmPtNc4Ma7BVTmTmFZOk2degbdi8a1si05bgz8iwqfgdRg 5ZBn7xmkjInQ+4uYg70kPczNeJ0OxlUDemX7Xu916CEcgcOPyh9CpRZm4XlAoIWPj0UzfK422 OmvkTlTLyt0bPObcvkwrx+A5aYEHanY1teyQzyfFgA0rms1jV9cN7muKjl0cSwYmWsPjZlW4j J2IpZUenNjro/lDe5hcUxuFMJcgVA/dIyv0LhZmP4GYCl5gGgWSjc7YYTbKFevf55VczRseYQ hF1uUoNBJ3xgvs7wjgC1u2IqOm8dSJa4EVvsMOb2NUbo9GKDDkOlWhcd26nB6G9iN6BOD6UdJ D/eJeoylYFNbJ7/dysjd3qdhKZxNRbKf3wZ2r1BU9OTfIad/4IuEfNvo8oFfXUktZMhg/9W/r oqkzTkjOyEFcPEkJ5pXlEoTvXNahWqAeOKDOFoH9P8eqznlAFRIlbGILksfGb9NiTCgRnHoew y9UziHaaoxzXVPcBGEJ75/4uNWSUhnAEnYezo2KQgBzsv7zwfc90OCBa/jPRBAK0oIwxeZ2tm gEdm/gf6cki+1tCl X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.134 Subject: [Qemu-devel] [PULL 2/7] target/m68k: add fmovecr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 fmovecr moves a floating point constant from the FPU ROM to a floating point register. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20170628204241.32106-3-laurent@vivier.eu> --- target/m68k/fpu_helper.c | 34 ++++++++++++++++++++++++++++++++++ target/m68k/helper.h | 1 + target/m68k/translate.c | 13 ++++++++++++- 3 files changed, 47 insertions(+), 1 deletion(-) diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index a9e17f5..4c14a1f 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -23,6 +23,35 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" =20 +/* Undefined offsets may be different on various FPU. + * On 68040 they return 0.0 (floatx80_zero) + */ + +static const floatx80 fpu_rom[128] =3D { + [0x00] =3D floatx80_pi, /* Pi */ + [0x0b] =3D make_floatx80(0x3ffd, 0x9a209a84fbcff798ULL), /* Log10(2) = */ + [0x0c] =3D make_floatx80(0x4000, 0xadf85458a2bb4a9aULL), /* e = */ + [0x0d] =3D make_floatx80(0x3fff, 0xb8aa3b295c17f0bcULL), /* Log2(e) = */ + [0x0e] =3D make_floatx80(0x3ffd, 0xde5bd8a937287195ULL), /* Log10(e) = */ + [0x0f] =3D floatx80_zero, /* Zero = */ + [0x30] =3D floatx80_ln2, /* ln(2) = */ + [0x31] =3D make_floatx80(0x4000, 0x935d8dddaaa8ac17ULL), /* ln(10) = */ + [0x32] =3D floatx80_one, /* 10^0 = */ + [0x33] =3D make_floatx80(0x4002, 0xa000000000000000ULL), /* 10^1 = */ + [0x34] =3D make_floatx80(0x4005, 0xc800000000000000ULL), /* 10^2 = */ + [0x35] =3D make_floatx80(0x400c, 0x9c40000000000000ULL), /* 10^4 = */ + [0x36] =3D make_floatx80(0x4019, 0xbebc200000000000ULL), /* 10^8 = */ + [0x37] =3D make_floatx80(0x4034, 0x8e1bc9bf04000000ULL), /* 10^16 = */ + [0x38] =3D make_floatx80(0x4069, 0x9dc5ada82b70b59eULL), /* 10^32 = */ + [0x39] =3D make_floatx80(0x40d3, 0xc2781f49ffcfa6d5ULL), /* 10^64 = */ + [0x3a] =3D make_floatx80(0x41a8, 0x93ba47c980e98ce0ULL), /* 10^128 = */ + [0x3b] =3D make_floatx80(0x4351, 0xaa7eebfb9df9de8eULL), /* 10^256 = */ + [0x3c] =3D make_floatx80(0x46a3, 0xe319a0aea60e91c7ULL), /* 10^512 = */ + [0x3d] =3D make_floatx80(0x4d48, 0xc976758681750c17ULL), /* 10^1024 = */ + [0x3e] =3D make_floatx80(0x5a92, 0x9e8b3b5dc53d5de5ULL), /* 10^2048 = */ + [0x3f] =3D make_floatx80(0x7525, 0xc46052028a20979bULL), /* 10^4096 = */ +}; + int32_t HELPER(reds32)(CPUM68KState *env, FPReg *val) { return floatx80_to_int32(val->d, &env->fp_status); @@ -204,3 +233,8 @@ void HELPER(ftst)(CPUM68KState *env, FPReg *val) } env->fpsr =3D (env->fpsr & ~FPSR_CC_MASK) | cc; } + +void HELPER(fconst)(CPUM68KState *env, FPReg *val, uint32_t offset) +{ + val->d =3D fpu_rom[offset]; +} diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 98cbf18..d6e80e4 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -35,6 +35,7 @@ DEF_HELPER_4(fdiv, void, env, fp, fp, fp) DEF_HELPER_FLAGS_3(fcmp, TCG_CALL_NO_RWG, void, env, fp, fp) DEF_HELPER_FLAGS_2(set_fpcr, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_2(ftst, TCG_CALL_NO_RWG, void, env, fp) +DEF_HELPER_3(fconst, void, env, fp, i32) =20 DEF_HELPER_3(mac_move, void, env, i32, i32) DEF_HELPER_3(macmulf, i64, env, i32, i32) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 5f4bedc..5b93d3f 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4518,10 +4518,21 @@ DISAS_INSN(fpu) ext =3D read_im16(env, s); opmode =3D ext & 0x7f; switch ((ext >> 13) & 7) { - case 0: case 2: + case 0: break; case 1: goto undef; + case 2: + if (insn =3D=3D 0xf200 && (ext & 0xfc00) =3D=3D 0x5c00) { + /* fmovecr */ + TCGv rom_offset =3D tcg_const_i32(opmode); + cpu_dest =3D gen_fp_ptr(REG(ext, 7)); + gen_helper_fconst(cpu_env, cpu_dest, rom_offset); + tcg_temp_free_ptr(cpu_dest); + tcg_temp_free(rom_offset); + return; + } + break; case 3: /* fmove out */ cpu_src =3D gen_fp_ptr(REG(ext, 7)); opsize =3D ext_opsize(ext, 10); --=20 2.9.4 From nobody Sat Apr 27 15:53:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498826100333883.3698568218332; Fri, 30 Jun 2017 05:35:00 -0700 (PDT) Received: from localhost ([::1]:44346 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQv8U-00030M-UZ for importer@patchew.org; Fri, 30 Jun 2017 08:34:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33281) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQv4g-00088C-97 for qemu-devel@nongnu.org; Fri, 30 Jun 2017 08:31:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQv4b-0005vl-7u for qemu-devel@nongnu.org; Fri, 30 Jun 2017 08:31:02 -0400 Received: from mout.kundenserver.de ([212.227.126.133]:56258) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dQv4a-0005s4-T8 for qemu-devel@nongnu.org; Fri, 30 Jun 2017 08:30:57 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue001 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MOG72-1dLQt72Iei-005ZML; Fri, 30 Jun 2017 14:30:53 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Fri, 30 Jun 2017 14:30:46 +0200 Message-Id: <20170630123050.19834-4-laurent@vivier.eu> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170630123050.19834-1-laurent@vivier.eu> References: <20170630123050.19834-1-laurent@vivier.eu> X-Provags-ID: V03:K0:HKs1MV/nqx3ui0nwy6pBooKABF9+lV41SNGaqMmo8fX2LJSWNML 9W3n4sGxzJkqvXNOek8DR81uCLN5KiNZ6Lq6izt7S4gck/Be6RyXxYUNLO8b18UkGD+460z qECJsIn5pwIOdL/oamp96sV9V3IswbR/uEsrVDYmBvCwFSe0nlQMJy/huAbor1gUgFWnrVK eNYfHRCS8iOXaCZVjhnPg== X-UI-Out-Filterresults: notjunk:1;V01:K0:Xy+Pg4g/CsI=:Hijm2KxOdHehUjg8dsgIk3 hkbH+rHY76QDXfBR1ucjgPcuXxDayUTpVHQfbCTOq2X3g6f02xlX9dXLuWBhQhdQUl2fg4xlc uh4XcGYmu7u6YhixxqdMvvYqKm9Yz2oqsrSCsOZ+7bXSRA7/M2Loz+AB9bAl13mnKoZEk8BV0 2f6kd+Czok0zl68wkyaUMVhOjA/uYR2qsi9WDLhYxALqjnExtXWDYTKb9fNE0D+AI8Bw4xx56 FE7zizbiAoS/U/CYj+tz0cs1uRDHYCch+ef+DNi7ULsJHIm+FsYtKyAe16Rz4gK6Z7SQT8Wy1 cbYp3gRV0fHSiB+c+z/JB28IdF0ldQgrEuvTQhqtvheaAxFSJU/8NnrjgD5+80dkgcLX84eHS OdkrSl5kRqbWhkx+55HFmXjR0IsxPe2x/hFx5upgQp/HguqCqONNjrr/li7JyDPmPGjaM/DzG bLbz6a7rhPb082HAzobBRQ7WB9QPtc6cI7SezCAgPX/tevfBNvrW8e5wMr6luFMeVESjbT8G6 5zGBwkHhxGZ+kBk/d/YABgnId0YO8yHNc+iEaYHlwnBvGl/CByA5cHKHOlguS86Dvkns268MC RI7QCl42NaGfPxOJUqIO2w/RNTmC79/qHj7tTn8/L0zU7A2dX2Ew/3RAd/X+rlMFdS8YXlkP7 6ZZGWnAoFegomLX9wdbXmCWbI+pWUsKjJaIeRK/BN8dvMRf43RqBgKMTwS0v3Ai5/IVQ= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.133 Subject: [Qemu-devel] [PULL 3/7] target/m68k: add explicit single and double precision operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add fssqrt, fdsqrt, fsadd, fdadd, fssub, fdsub, fsmul, fdmul, fsdiv, fddiv. The precision is managed using set_floatx80_rounding_precision(). Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20170628204241.32106-4-laurent@vivier.eu> --- target/m68k/fpu_helper.c | 80 ++++++++++++++++++++++++++++++++++++++++++++= ++++ target/m68k/helper.h | 10 ++++++ target/m68k/translate.c | 40 +++++++++++++++++++++--- 3 files changed, 125 insertions(+), 5 deletions(-) diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index 4c14a1f..3b53554 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -157,11 +157,35 @@ void HELPER(set_fpcr)(CPUM68KState *env, uint32_t val) cpu_m68k_set_fpcr(env, val); } =20 +#define PREC_BEGIN(prec) \ + do { \ + int old; \ + old =3D get_floatx80_rounding_precision(&env->fp_status); \ + set_floatx80_rounding_precision(prec, &env->fp_status) \ + +#define PREC_END() \ + set_floatx80_rounding_precision(old, &env->fp_status); \ + } while (0) + void HELPER(fsqrt)(CPUM68KState *env, FPReg *res, FPReg *val) { res->d =3D floatx80_sqrt(val->d, &env->fp_status); } =20 +void HELPER(fssqrt)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + PREC_BEGIN(32); + res->d =3D floatx80_sqrt(val->d, &env->fp_status); + PREC_END(); +} + +void HELPER(fdsqrt)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + PREC_BEGIN(64); + res->d =3D floatx80_sqrt(val->d, &env->fp_status); + PREC_END(); +} + void HELPER(fabs)(CPUM68KState *env, FPReg *res, FPReg *val) { res->d =3D floatx80_abs(val->d); @@ -177,21 +201,77 @@ void HELPER(fadd)(CPUM68KState *env, FPReg *res, FPRe= g *val0, FPReg *val1) res->d =3D floatx80_add(val0->d, val1->d, &env->fp_status); } =20 +void HELPER(fsadd)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) +{ + PREC_BEGIN(32); + res->d =3D floatx80_add(val0->d, val1->d, &env->fp_status); + PREC_END(); +} + +void HELPER(fdadd)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) +{ + PREC_BEGIN(64); + res->d =3D floatx80_add(val0->d, val1->d, &env->fp_status); + PREC_END(); +} + void HELPER(fsub)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) { res->d =3D floatx80_sub(val1->d, val0->d, &env->fp_status); } =20 +void HELPER(fssub)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) +{ + PREC_BEGIN(32); + res->d =3D floatx80_sub(val1->d, val0->d, &env->fp_status); + PREC_END(); +} + +void HELPER(fdsub)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) +{ + PREC_BEGIN(64); + res->d =3D floatx80_sub(val1->d, val0->d, &env->fp_status); + PREC_END(); +} + void HELPER(fmul)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) { res->d =3D floatx80_mul(val0->d, val1->d, &env->fp_status); } =20 +void HELPER(fsmul)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) +{ + PREC_BEGIN(32); + res->d =3D floatx80_mul(val0->d, val1->d, &env->fp_status); + PREC_END(); +} + +void HELPER(fdmul)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) +{ + PREC_BEGIN(64); + res->d =3D floatx80_mul(val0->d, val1->d, &env->fp_status); + PREC_END(); +} + void HELPER(fdiv)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) { res->d =3D floatx80_div(val1->d, val0->d, &env->fp_status); } =20 +void HELPER(fsdiv)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) +{ + PREC_BEGIN(32); + res->d =3D floatx80_div(val1->d, val0->d, &env->fp_status); + PREC_END(); +} + +void HELPER(fddiv)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) +{ + PREC_BEGIN(64); + res->d =3D floatx80_div(val1->d, val0->d, &env->fp_status); + PREC_END(); +} + static int float_comp_to_cc(int float_compare) { switch (float_compare) { diff --git a/target/m68k/helper.h b/target/m68k/helper.h index d6e80e4..0c7f06f 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -26,12 +26,22 @@ DEF_HELPER_2(reds32, s32, env, fp) DEF_HELPER_3(firound, void, env, fp, fp) DEF_HELPER_3(fitrunc, void, env, fp, fp) DEF_HELPER_3(fsqrt, void, env, fp, fp) +DEF_HELPER_3(fssqrt, void, env, fp, fp) +DEF_HELPER_3(fdsqrt, void, env, fp, fp) DEF_HELPER_3(fabs, void, env, fp, fp) DEF_HELPER_3(fchs, void, env, fp, fp) DEF_HELPER_4(fadd, void, env, fp, fp, fp) +DEF_HELPER_4(fsadd, void, env, fp, fp, fp) +DEF_HELPER_4(fdadd, void, env, fp, fp, fp) DEF_HELPER_4(fsub, void, env, fp, fp, fp) +DEF_HELPER_4(fssub, void, env, fp, fp, fp) +DEF_HELPER_4(fdsub, void, env, fp, fp, fp) DEF_HELPER_4(fmul, void, env, fp, fp, fp) +DEF_HELPER_4(fsmul, void, env, fp, fp, fp) +DEF_HELPER_4(fdmul, void, env, fp, fp, fp) DEF_HELPER_4(fdiv, void, env, fp, fp, fp) +DEF_HELPER_4(fsdiv, void, env, fp, fp, fp) +DEF_HELPER_4(fddiv, void, env, fp, fp, fp) DEF_HELPER_FLAGS_3(fcmp, TCG_CALL_NO_RWG, void, env, fp, fp) DEF_HELPER_FLAGS_2(set_fpcr, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_2(ftst, TCG_CALL_NO_RWG, void, env, fp) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 5b93d3f..618abf6 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4604,27 +4604,57 @@ DISAS_INSN(fpu) case 3: /* fintrz */ gen_helper_fitrunc(cpu_env, cpu_dest, cpu_src); break; - case 4: case 0x41: case 0x45: /* fsqrt */ + case 4: /* fsqrt */ gen_helper_fsqrt(cpu_env, cpu_dest, cpu_src); break; + case 0x41: /* fssqrt */ + gen_helper_fssqrt(cpu_env, cpu_dest, cpu_src); + break; + case 0x45: /* fdsqrt */ + gen_helper_fdsqrt(cpu_env, cpu_dest, cpu_src); + break; case 0x18: case 0x58: case 0x5c: /* fabs */ gen_helper_fabs(cpu_env, cpu_dest, cpu_src); break; case 0x1a: case 0x5a: case 0x5e: /* fneg */ gen_helper_fchs(cpu_env, cpu_dest, cpu_src); break; - case 0x20: case 0x60: case 0x64: /* fdiv */ + case 0x20: /* fdiv */ gen_helper_fdiv(cpu_env, cpu_dest, cpu_src, cpu_dest); break; - case 0x22: case 0x62: case 0x66: /* fadd */ + case 0x60: /* fsdiv */ + gen_helper_fsdiv(cpu_env, cpu_dest, cpu_src, cpu_dest); + break; + case 0x64: /* fddiv */ + gen_helper_fddiv(cpu_env, cpu_dest, cpu_src, cpu_dest); + break; + case 0x22: /* fadd */ gen_helper_fadd(cpu_env, cpu_dest, cpu_src, cpu_dest); break; - case 0x23: case 0x63: case 0x67: /* fmul */ + case 0x62: /* fsadd */ + gen_helper_fsadd(cpu_env, cpu_dest, cpu_src, cpu_dest); + break; + case 0x66: /* fdadd */ + gen_helper_fdadd(cpu_env, cpu_dest, cpu_src, cpu_dest); + break; + case 0x23: /* fmul */ gen_helper_fmul(cpu_env, cpu_dest, cpu_src, cpu_dest); break; - case 0x28: case 0x68: case 0x6c: /* fsub */ + case 0x63: /* fsmul */ + gen_helper_fsmul(cpu_env, cpu_dest, cpu_src, cpu_dest); + break; + case 0x67: /* fdmul */ + gen_helper_fdmul(cpu_env, cpu_dest, cpu_src, cpu_dest); + break; + case 0x28: /* fsub */ gen_helper_fsub(cpu_env, cpu_dest, cpu_src, cpu_dest); break; + case 0x68: /* fssub */ + gen_helper_fssub(cpu_env, cpu_dest, cpu_src, cpu_dest); + break; + case 0x6c: /* fdsub */ + gen_helper_fdsub(cpu_env, cpu_dest, cpu_src, cpu_dest); + break; case 0x38: /* fcmp */ gen_helper_fcmp(cpu_env, cpu_src, cpu_dest); return; --=20 2.9.4 From nobody Sat Apr 27 15:53:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149882609325182.84081584282956; Fri, 30 Jun 2017 05:34:53 -0700 (PDT) Received: from localhost ([::1]:44345 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQv8M-0002sr-Rr for importer@patchew.org; Fri, 30 Jun 2017 08:34:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33284) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQv4g-0008Aa-PV for qemu-devel@nongnu.org; Fri, 30 Jun 2017 08:31:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQv4a-0005uv-Vx for qemu-devel@nongnu.org; Fri, 30 Jun 2017 08:31:02 -0400 Received: from mout.kundenserver.de ([212.227.126.131]:56310) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dQv4a-0005sP-CP for qemu-devel@nongnu.org; Fri, 30 Jun 2017 08:30:56 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue001 [212.227.15.167]) with ESMTPSA (Nemesis) id 0LmT7D-1dzz2b07Yh-00aFgI; Fri, 30 Jun 2017 14:30:54 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Fri, 30 Jun 2017 14:30:47 +0200 Message-Id: <20170630123050.19834-5-laurent@vivier.eu> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170630123050.19834-1-laurent@vivier.eu> References: <20170630123050.19834-1-laurent@vivier.eu> X-Provags-ID: V03:K0:iZgoKiJgU88Mlz6yhHFiLbAtWBfDtWuZhuC4MMv9KXEhYPMJ579 MNeSWPHLdbY9HGVlS3Q/qf2vZCBH9VkhV11T8++V7LQsHPZ1ZLwI/9VTOJn0zE9mEJLS0h3 Y23w6JTW4ZvCXjEdcwskgBp737l2mZSNgEAW6nlDlVNOCKpRvu6AFvgxcqfWUeLiYrZaQ8n BS78szmgY98U7LrYiw4Hw== X-UI-Out-Filterresults: notjunk:1;V01:K0:GW6Vf8RAZiM=:RzKs6qy2fa2uwJsse0006i sTx4mEAgn6hk3rLgXzKdawbB6gqWZjAQDzi7LtybyTPs5hlrbMDMHVtQayGtkuCoz8prn52UW NBwU0BDToqQzrxto+r5WTgR3z4Aqw/Na1IpNr5q98AwSL5qBPLxSqVRaiAiHkSn+g6+3Yjgkx g1umKVxi3V6yu3oO1IwsGuoqxm8NWJGW/xVXjvKmSgGqZ4isecTjz6xfDn59ZhhZRvgVp7FLw EcQX8KM7p7wfsD837NftUt87KK2lH2w2rmT/Y9ECqNM+GThUBxh60JVvBJ9F7RDSy14xmLG0O 6xLQWKCtjYZfpDoHTagJbC96GQX7YolIs6RhTEHam8o2B7HWmIR69f8517vhVPrQmy8vCzdv5 ltgmqS2UxfZR3fLSRnEcLyfavYzgNE71iUF/hx6I8ZMSvAPAEWBixElGLkj9SXV0zvdP+k6zh NSjirjlQNJbBXGmUis/S+bXv1QZRoh/ub6BeITc1RnnbgYzpUjGxa6U9D6k6fSx72HQ+4SX95 r6UBBXzBRfYdOpbfK8yca5hg4eFpgdq1dB67k4au4UC3tsH8eqR/BgFyr+8bXEE0UtDNmStE7 ZGZMugTg8XhUxt6Oi7ZE9pi4fwVHXw9gCtCASqyt8vUSOVCK3dh0Y0OtZNLXCnGXGvmCeZDRw jhwv+klThV09Uu/HYmU93p/xOzY+23M6lTUpS0iAJFnRSGDf6afcLsR+rNyVgf1oCDI4= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.131 Subject: [Qemu-devel] [PULL 4/7] softfloat: define floatx80_round() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add a function to round a floatx80 to the defined precision (floatx80_rounding_precision) Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Reviewed-by: Aurelien Jarno Message-Id: <20170628204241.32106-5-laurent@vivier.eu> --- fpu/softfloat.c | 16 ++++++++++++++++ include/fpu/softfloat.h | 1 + 2 files changed, 17 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 7af14e2..433c5da 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -5086,6 +5086,22 @@ float128 floatx80_to_float128(floatx80 a, float_stat= us *status) } =20 /*------------------------------------------------------------------------= ---- +| Rounds the extended double-precision floating-point value `a' +| to the precision provided by floatx80_rounding_precision and returns the +| result as an extended double-precision floating-point value. +| The operation is performed according to the IEC/IEEE Standard for Binary +| Floating-Point Arithmetic. +*-------------------------------------------------------------------------= ---*/ + +floatx80 floatx80_round(floatx80 a, float_status *status) +{ + return roundAndPackFloatx80(status->floatx80_rounding_precision, + extractFloatx80Sign(a), + extractFloatx80Exp(a), + extractFloatx80Frac(a), 0, status); +} + +/*------------------------------------------------------------------------= ---- | Rounds the extended double-precision floating-point value `a' to an inte= ger, | and returns the result as an extended quadruple-precision floating-point | value. The operation is performed according to the IEC/IEEE Standard for diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index f1288ef..d9689ec 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -621,6 +621,7 @@ float128 floatx80_to_float128(floatx80, float_status *s= tatus); /*------------------------------------------------------------------------= ---- | Software IEC/IEEE extended double-precision operations. *-------------------------------------------------------------------------= ---*/ +floatx80 floatx80_round(floatx80 a, float_status *status); floatx80 floatx80_round_to_int(floatx80, float_status *status); floatx80 floatx80_add(floatx80, floatx80, float_status *status); floatx80 floatx80_sub(floatx80, floatx80, float_status *status); --=20 2.9.4 From nobody Sat Apr 27 15:53:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498826219416806.3191946491664; Fri, 30 Jun 2017 05:36:59 -0700 (PDT) Received: from localhost ([::1]:44359 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQvAP-0004WK-32 for importer@patchew.org; Fri, 30 Jun 2017 08:36:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33300) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQv4h-0008C6-GC for qemu-devel@nongnu.org; Fri, 30 Jun 2017 08:31:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQv4a-0005th-Fz for qemu-devel@nongnu.org; Fri, 30 Jun 2017 08:31:03 -0400 Received: from mout.kundenserver.de ([212.227.126.134]:51937) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dQv4a-0005sN-3G for qemu-devel@nongnu.org; Fri, 30 Jun 2017 08:30:56 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue001 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MeXgF-1d5hYH1mhz-00Q8LW; Fri, 30 Jun 2017 14:30:54 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Fri, 30 Jun 2017 14:30:48 +0200 Message-Id: <20170630123050.19834-6-laurent@vivier.eu> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170630123050.19834-1-laurent@vivier.eu> References: <20170630123050.19834-1-laurent@vivier.eu> X-Provags-ID: V03:K0:xURLmGrnh+zq/vlAl79ki7MZj8xdv3IqqdMGYDgM8Y7uiYhpAqK SurpM3hLh5qRdc2hC7/kD+0QRD2Nj9x/1DLMlfBWfq2lE4+5oz1d4uLm6fnRQu7F687lRTL HU97E9CPxrUYgxtApAhv5h635CBTq/MhtP3owddkOiPSarVZ27Lh1XNBM+UWab3180od9ma G8a9k2hVFOfc5E/yE4Vjw== X-UI-Out-Filterresults: notjunk:1;V01:K0:/Ke0hPiT8pM=:6U84ORZOjwIYzWD8E8m5yX 5MUyrz7O+L5OB0qPja0yeIkHP/N56VATHWAADmuyZ2mp16PUiUib702TPE/LjzQh+VmE/agaB ku9SoUOTLE2/rkbPrO/1MXmVw/KgpVuuVRijg+cLzL6zCQgDJb9jE6zumz2E2orMFIP/Y/3ya fBKqsCTnEK4JSqBYAQhaPe0cmeinOuXgFYImJFOcbF7q39PX5UraWjiYRg1y/Dr1Vu0Gw7zMS 8utyoTKFhMbfmSzdRTCMj/3rP3V2a19XfmKcGPLMOegi1AizhNubrYx0Wy11yHwq3ZxzYdMWS 9+7cyCWHME/nf0oPo4JNm8e7nyL/xoV3mFFkr+LxIqzW9Spa9QyzwuJcAmHZy7rBtdt4HWcox U3G8dLa+Sx82MDYX0VabIzs0nMZihgtmP2wB4JfDmBl4mu3BTczG89+1r92VgcIvv9YNRKf5t /+nCrGpg79h6pYtaybXDFNuHQgVe8mef6eFhMAIzJFggyZfiTeG6M9EEebpz99X+hnMNj2zeh TrBB5iOSHyB4ln4kMudU6Y48xKj3F+G/dGw9KvnuG6hLFSeZcCAOSrqHCEd3Ej3beR0Qhjsfl IQdmPk71zrjHLxt9eqHPEoANzwmDj/D9MPgmZDH1HVtL1iSgn+8XKHVDk5jwJhSENedbNVzu2 s0WGLlasIxk84gdlsGifmJNCv4gzHtWE5i7UxfUC65Nsgp7YdOdyV+IVtiOZGv2r/o58= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.134 Subject: [Qemu-devel] [PULL 5/7] target/m68k: add fsglmul and fsgldiv X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" fsglmul and fsgldiv truncate data to single precision before computing results. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20170628204241.32106-6-laurent@vivier.eu> --- target/m68k/fpu_helper.c | 28 ++++++++++++++++++++++++++++ target/m68k/helper.h | 2 ++ target/m68k/translate.c | 6 ++++++ 3 files changed, 36 insertions(+) diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index 3b53554..600ae8a 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -253,6 +253,20 @@ void HELPER(fdmul)(CPUM68KState *env, FPReg *res, FPRe= g *val0, FPReg *val1) PREC_END(); } =20 +void HELPER(fsglmul)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *va= l1) +{ + int rounding_mode =3D get_float_rounding_mode(&env->fp_status); + floatx80 a, b; + + PREC_BEGIN(32); + set_float_rounding_mode(float_round_to_zero, &env->fp_status); + a =3D floatx80_round(val0->d, &env->fp_status); + b =3D floatx80_round(val1->d, &env->fp_status); + set_float_rounding_mode(rounding_mode, &env->fp_status); + res->d =3D floatx80_mul(a, b, &env->fp_status); + PREC_END(); +} + void HELPER(fdiv)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) { res->d =3D floatx80_div(val1->d, val0->d, &env->fp_status); @@ -272,6 +286,20 @@ void HELPER(fddiv)(CPUM68KState *env, FPReg *res, FPRe= g *val0, FPReg *val1) PREC_END(); } =20 +void HELPER(fsgldiv)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *va= l1) +{ + int rounding_mode =3D get_float_rounding_mode(&env->fp_status); + floatx80 a, b; + + PREC_BEGIN(32); + set_float_rounding_mode(float_round_to_zero, &env->fp_status); + a =3D floatx80_round(val1->d, &env->fp_status); + b =3D floatx80_round(val0->d, &env->fp_status); + set_float_rounding_mode(rounding_mode, &env->fp_status); + res->d =3D floatx80_div(a, b, &env->fp_status); + PREC_END(); +} + static int float_comp_to_cc(int float_compare) { switch (float_compare) { diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 0c7f06f..f05191b 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -39,9 +39,11 @@ DEF_HELPER_4(fdsub, void, env, fp, fp, fp) DEF_HELPER_4(fmul, void, env, fp, fp, fp) DEF_HELPER_4(fsmul, void, env, fp, fp, fp) DEF_HELPER_4(fdmul, void, env, fp, fp, fp) +DEF_HELPER_4(fsglmul, void, env, fp, fp, fp) DEF_HELPER_4(fdiv, void, env, fp, fp, fp) DEF_HELPER_4(fsdiv, void, env, fp, fp, fp) DEF_HELPER_4(fddiv, void, env, fp, fp, fp) +DEF_HELPER_4(fsgldiv, void, env, fp, fp, fp) DEF_HELPER_FLAGS_3(fcmp, TCG_CALL_NO_RWG, void, env, fp, fp) DEF_HELPER_FLAGS_2(set_fpcr, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_2(ftst, TCG_CALL_NO_RWG, void, env, fp) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 618abf6..72c45de 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4646,6 +4646,12 @@ DISAS_INSN(fpu) case 0x67: /* fdmul */ gen_helper_fdmul(cpu_env, cpu_dest, cpu_src, cpu_dest); break; + case 0x24: /* fsgldiv */ + gen_helper_fsgldiv(cpu_env, cpu_dest, cpu_src, cpu_dest); + break; + case 0x27: /* fsglmul */ + gen_helper_fsglmul(cpu_env, cpu_dest, cpu_src, cpu_dest); + break; case 0x28: /* fsub */ gen_helper_fsub(cpu_env, cpu_dest, cpu_src, cpu_dest); break; --=20 2.9.4 From nobody Sat Apr 27 15:53:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498825967319931.205102585021; Fri, 30 Jun 2017 05:32:47 -0700 (PDT) Received: from localhost ([::1]:44340 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQv6K-0000dq-Jq for importer@patchew.org; Fri, 30 Jun 2017 08:32:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33288) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQv4h-0008Bl-1g for qemu-devel@nongnu.org; Fri, 30 Jun 2017 08:31:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQv4a-0005v1-W8 for qemu-devel@nongnu.org; Fri, 30 Jun 2017 08:31:03 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:60152) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dQv4a-0005sW-FW for qemu-devel@nongnu.org; Fri, 30 Jun 2017 08:30:56 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue001 [212.227.15.167]) with ESMTPSA (Nemesis) id 0Mh1yy-1d4rwU3PGa-00M0HR; Fri, 30 Jun 2017 14:30:55 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Fri, 30 Jun 2017 14:30:49 +0200 Message-Id: <20170630123050.19834-7-laurent@vivier.eu> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170630123050.19834-1-laurent@vivier.eu> References: <20170630123050.19834-1-laurent@vivier.eu> X-Provags-ID: V03:K0:QbcMrbR9T3m5Tyk83o87ewZKf/XWyPwnvnShr2RCDQ4Z/eNt8J7 W4xRGW7CfF59CDkedKzimxOy8Y7Z86Yw0TFlpVKc+SGWGt+fj261F6JjWKKB57ev3Z9Qg44 QjTsr6vLQFWNkj2+9IzLk6pBcRj0X1LdhoW61kATD4ZQG/ykl8evyIBMk9jyItfS6En/vzT R9zlxFzCJzQSS4c/4KBqg== X-UI-Out-Filterresults: notjunk:1;V01:K0:yTVbgbP/A4w=:OJU4M5QcY0514cVlttwYgW nBJaMr60mBtlqZT8JThMwLC0FtdEY3/2zN8I4NZT7sAPmwQy+qkEdRRYf+Oodr+vS3yRkBwfa IMtFIh7lmwU3Kh9DWEioU1Rkobpiaa/LGiPc9lzMaCRTcvSHhIawU2J/xCbvc3gHAcs8L1sC2 G0w3/FrcPlPkOJY4EBGppiWHBZ6m8lmDZp6hXMw483N+edpHzhKN7bMeddpKa8aNaLXw4RXfj ihp9tsTqhL86xie5Hod/jugt8YsQD1GSeNQ3dbq4/7cotA2pW8LwOYAZjGO4PMf3IZ940LGNN 4yHcm8OHLAN3Ku/+EfqYdqjEp+3nAUNqQ8ooJTUMWLguUw6rN0hXmGWV/G+95qZp6KVOMvQOM KE7GSAnPU557OJe9AKwtFoYV/PkRSggszPzjgqZfbP5mub/YRi4TkHD/rAThJaCDCehzuIr7x +ZLktVv9AgjXegy2aSS3QzXg3SzFXNvyiivjBdIO7YfnFNPEkTwW9HIRzOExytb6JE//K9DqS DkQbpfaxJZCChgO6wPYPbeh733NEIA98XzO3CPRqEqvXNdAjpboaUTaqpOJG9u9Cj+BJxFSiN fkbDOys6UctF4qSLI9B2nyIHCc5oCITRcEfpENXSBKD+IzCdoh9ONaETCCHaC73NhaSw6oBpo BA9kmkXcK+0GKBkfpYXqO/XSOtwOJ9AWO18o92E+5JRytzXK2MuCpDo+FbryI9UGSilg= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [PULL 6/7] target/m68k: add explicit single and double precision operations (part 2) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add fsabs, fdabs, fsneg, fdneg, fsmove and fdmove. The value is converted using the new floatx80_round() function. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20170628204241.32106-7-laurent@vivier.eu> --- target/m68k/fpu_helper.c | 48 ++++++++++++++++++++++++++++++++++++++++++++= +--- target/m68k/helper.h | 8 +++++++- target/m68k/translate.c | 26 ++++++++++++++++++++++---- 3 files changed, 74 insertions(+), 8 deletions(-) diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index 600ae8a..382fbc1 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -167,6 +167,20 @@ void HELPER(set_fpcr)(CPUM68KState *env, uint32_t val) set_floatx80_rounding_precision(old, &env->fp_status); \ } while (0) =20 +void HELPER(fsround)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + PREC_BEGIN(32); + res->d =3D floatx80_round(val->d, &env->fp_status); + PREC_END(); +} + +void HELPER(fdround)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + PREC_BEGIN(64); + res->d =3D floatx80_round(val->d, &env->fp_status); + PREC_END(); +} + void HELPER(fsqrt)(CPUM68KState *env, FPReg *res, FPReg *val) { res->d =3D floatx80_sqrt(val->d, &env->fp_status); @@ -188,12 +202,40 @@ void HELPER(fdsqrt)(CPUM68KState *env, FPReg *res, FP= Reg *val) =20 void HELPER(fabs)(CPUM68KState *env, FPReg *res, FPReg *val) { - res->d =3D floatx80_abs(val->d); + res->d =3D floatx80_round(floatx80_abs(val->d), &env->fp_status); +} + +void HELPER(fsabs)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + PREC_BEGIN(32); + res->d =3D floatx80_round(floatx80_abs(val->d), &env->fp_status); + PREC_END(); +} + +void HELPER(fdabs)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + PREC_BEGIN(64); + res->d =3D floatx80_round(floatx80_abs(val->d), &env->fp_status); + PREC_END(); +} + +void HELPER(fneg)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + res->d =3D floatx80_round(floatx80_chs(val->d), &env->fp_status); } =20 -void HELPER(fchs)(CPUM68KState *env, FPReg *res, FPReg *val) +void HELPER(fsneg)(CPUM68KState *env, FPReg *res, FPReg *val) { - res->d =3D floatx80_chs(val->d); + PREC_BEGIN(32); + res->d =3D floatx80_round(floatx80_chs(val->d), &env->fp_status); + PREC_END(); +} + +void HELPER(fdneg)(CPUM68KState *env, FPReg *res, FPReg *val) +{ + PREC_BEGIN(64); + res->d =3D floatx80_round(floatx80_chs(val->d), &env->fp_status); + PREC_END(); } =20 void HELPER(fadd)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) diff --git a/target/m68k/helper.h b/target/m68k/helper.h index f05191b..b396899 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -23,13 +23,19 @@ DEF_HELPER_2(redf32, f32, env, fp) DEF_HELPER_2(redf64, f64, env, fp) DEF_HELPER_2(reds32, s32, env, fp) =20 +DEF_HELPER_3(fsround, void, env, fp, fp) +DEF_HELPER_3(fdround, void, env, fp, fp) DEF_HELPER_3(firound, void, env, fp, fp) DEF_HELPER_3(fitrunc, void, env, fp, fp) DEF_HELPER_3(fsqrt, void, env, fp, fp) DEF_HELPER_3(fssqrt, void, env, fp, fp) DEF_HELPER_3(fdsqrt, void, env, fp, fp) DEF_HELPER_3(fabs, void, env, fp, fp) -DEF_HELPER_3(fchs, void, env, fp, fp) +DEF_HELPER_3(fsabs, void, env, fp, fp) +DEF_HELPER_3(fdabs, void, env, fp, fp) +DEF_HELPER_3(fneg, void, env, fp, fp) +DEF_HELPER_3(fsneg, void, env, fp, fp) +DEF_HELPER_3(fdneg, void, env, fp, fp) DEF_HELPER_4(fadd, void, env, fp, fp, fp) DEF_HELPER_4(fsadd, void, env, fp, fp, fp) DEF_HELPER_4(fdadd, void, env, fp, fp, fp) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 72c45de..89ac2c7 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4595,9 +4595,15 @@ DISAS_INSN(fpu) } cpu_dest =3D gen_fp_ptr(REG(ext, 7)); switch (opmode) { - case 0: case 0x40: case 0x44: /* fmove */ + case 0: /* fmove */ gen_fp_move(cpu_dest, cpu_src); break; + case 0x40: /* fsmove */ + gen_helper_fsround(cpu_env, cpu_dest, cpu_src); + break; + case 0x44: /* fdmove */ + gen_helper_fdround(cpu_env, cpu_dest, cpu_src); + break; case 1: /* fint */ gen_helper_firound(cpu_env, cpu_dest, cpu_src); break; @@ -4613,11 +4619,23 @@ DISAS_INSN(fpu) case 0x45: /* fdsqrt */ gen_helper_fdsqrt(cpu_env, cpu_dest, cpu_src); break; - case 0x18: case 0x58: case 0x5c: /* fabs */ + case 0x18: /* fabs */ gen_helper_fabs(cpu_env, cpu_dest, cpu_src); break; - case 0x1a: case 0x5a: case 0x5e: /* fneg */ - gen_helper_fchs(cpu_env, cpu_dest, cpu_src); + case 0x58: /* fsabs */ + gen_helper_fsabs(cpu_env, cpu_dest, cpu_src); + break; + case 0x5c: /* fdabs */ + gen_helper_fdabs(cpu_env, cpu_dest, cpu_src); + break; + case 0x1a: /* fneg */ + gen_helper_fneg(cpu_env, cpu_dest, cpu_src); + break; + case 0x5a: /* fsneg */ + gen_helper_fsneg(cpu_env, cpu_dest, cpu_src); + break; + case 0x5e: /* fdneg */ + gen_helper_fdneg(cpu_env, cpu_dest, cpu_src); break; case 0x20: /* fdiv */ gen_helper_fdiv(cpu_env, cpu_dest, cpu_src, cpu_dest); --=20 2.9.4 From nobody Sat Apr 27 15:53:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498826101609909.4726418917671; Fri, 30 Jun 2017 05:35:01 -0700 (PDT) Received: from localhost ([::1]:44347 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQv8W-00031G-4v for importer@patchew.org; Fri, 30 Jun 2017 08:35:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33293) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQv4h-0008Bu-7z for qemu-devel@nongnu.org; Fri, 30 Jun 2017 08:31:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQv4b-0005wJ-F1 for qemu-devel@nongnu.org; Fri, 30 Jun 2017 08:31:03 -0400 Received: from mout.kundenserver.de ([212.227.126.131]:54506) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dQv4b-0005sr-2j for qemu-devel@nongnu.org; Fri, 30 Jun 2017 08:30:57 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue001 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MPuXS-1dLzO110s6-0051f1; Fri, 30 Jun 2017 14:30:55 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Fri, 30 Jun 2017 14:30:50 +0200 Message-Id: <20170630123050.19834-8-laurent@vivier.eu> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170630123050.19834-1-laurent@vivier.eu> References: <20170630123050.19834-1-laurent@vivier.eu> X-Provags-ID: V03:K0:f4KI6nPX6yzYFvLE1JXYIlb8EBoGhj/BrW7WNjJ9u9r1/5uo//S u4g+AyoEezptoCw+NpZT7qQTFWKE070TaT6DVoY3VsiQpVxXSsn3xZR5vm8DqMJ550xUnMI 0wTJjRhIq9z/VLTkN5TGWMtHc5Qf86NpQH+KJG4Y9JW+lE/9ihwm5PWmdWGsX24nNBzmV/J kMw60TfgxLAhP2VLDgxOQ== X-UI-Out-Filterresults: notjunk:1;V01:K0:7CgJ7jVLp1s=:qYAtNBNwL8VhmBrSUUybMg kdnG5VuqCPiJnjy8XWI/ji2n/08k84YyK6dX4T6eUIEiDOhUrAOb+c5zgBZ8vtYEY+XuEuN2P thdBLTv8i7DYXexLyecblRVd8ws5LzfvqX09l0gMLAijaf3MkwTnCa3kbgkyg/jV4VlPujkoA kGV+rF8BJLl0olomd8jo44wZANY+5vUGCdJL629aU5xeEeUnUDOjCq/hrp3kS6tcmMX/AsB+L GOB5zs8ZYyDzLNV1m0xNCw1KPTyIiGXy/6iM003+kKN0ana+EFd2PnNxc7mMWc32sjny0fMNC ac8NZD8qv5Er/EBVI8soTtcNEGdw4NqmXgaLlt12QSur25TlolqSaBKa4WaFul0KY09SjqQ80 sEGQEdNnZy0eLBd8zjMhxE+H5ZdPPWQfrdfCL4B6rZva29rHxzg2Q4DnD5TKKQYtZfGt4LtaM eX0qVJuE2MFkfZihJyWq9ikqOqHEWAdbaTb7V9gzefjQesv0qD64lXMkAmEnRJpAZA04VSLlH rWiVC3Yxmk5OOZFj6Ai74QwnAo62UNQjFIsxjPCHO03K6ukRZj0HFokIUbV79GYrSil+87YUg acF2+L0y38+0IZf2BcaXvrh96PrfFsTLCsbgYq6NIoNUH0+x7ZWYbem5r5gftSkkrMd0zO05j 0318BO3bp+XAlvIkY4+TugafCYHoZjcFokzXYC9YRHWbPFKwwwWBv5uWyDkH0/wB8LPk= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.131 Subject: [Qemu-devel] [PULL 7/7] target/m68k: add fmovem X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20170628204241.32106-8-laurent@vivier.eu> --- target/m68k/fpu_helper.c | 120 +++++++++++++++++++++++++++++++++++++++++++= ++++ target/m68k/helper.h | 6 +++ target/m68k/translate.c | 93 ++++++++++++++++++++++++------------ 3 files changed, 189 insertions(+), 30 deletions(-) diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index 382fbc1..bdfc537 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/cpu_ldst.h" =20 /* Undefined offsets may be different on various FPU. * On 68040 they return 0.0 (floatx80_zero) @@ -388,3 +389,122 @@ void HELPER(fconst)(CPUM68KState *env, FPReg *val, ui= nt32_t offset) { val->d =3D fpu_rom[offset]; } + +typedef int (*float_access)(CPUM68KState *env, uint32_t addr, FPReg *fp, + uintptr_t ra); + +static uint32_t fmovem_predec(CPUM68KState *env, uint32_t addr, uint32_t m= ask, + float_access access) +{ + uintptr_t ra =3D GETPC(); + int i, size; + + for (i =3D 7; i >=3D 0; i--, mask <<=3D 1) { + if (mask & 0x80) { + size =3D access(env, addr, &env->fregs[i], ra); + if ((mask & 0xff) !=3D 0x80) { + addr -=3D size; + } + } + } + + return addr; +} + +static uint32_t fmovem_postinc(CPUM68KState *env, uint32_t addr, uint32_t = mask, + float_access access) +{ + uintptr_t ra =3D GETPC(); + int i, size; + + for (i =3D 0; i < 8; i++, mask <<=3D 1) { + if (mask & 0x80) { + size =3D access(env, addr, &env->fregs[i], ra); + addr +=3D size; + } + } + + return addr; +} + +static int cpu_ld_floatx80_ra(CPUM68KState *env, uint32_t addr, FPReg *fp, + uintptr_t ra) +{ + uint32_t high; + uint64_t low; + + high =3D cpu_ldl_data_ra(env, addr, ra); + low =3D cpu_ldq_data_ra(env, addr + 4, ra); + + fp->l.upper =3D high >> 16; + fp->l.lower =3D low; + + return 12; +} + +static int cpu_st_floatx80_ra(CPUM68KState *env, uint32_t addr, FPReg *fp, + uintptr_t ra) +{ + cpu_stl_data_ra(env, addr, fp->l.upper << 16, ra); + cpu_stq_data_ra(env, addr + 4, fp->l.lower, ra); + + return 12; +} + +static int cpu_ld_float64_ra(CPUM68KState *env, uint32_t addr, FPReg *fp, + uintptr_t ra) +{ + uint64_t val; + + val =3D cpu_ldq_data_ra(env, addr, ra); + fp->d =3D float64_to_floatx80(*(float64 *)&val, &env->fp_status); + + return 8; +} + +static int cpu_st_float64_ra(CPUM68KState *env, uint32_t addr, FPReg *fp, + uintptr_t ra) +{ + float64 val; + + val =3D floatx80_to_float64(fp->d, &env->fp_status); + cpu_stq_data_ra(env, addr, *(uint64_t *)&val, ra); + + return 8; +} + +uint32_t HELPER(fmovemx_st_predec)(CPUM68KState *env, uint32_t addr, + uint32_t mask) +{ + return fmovem_predec(env, addr, mask, cpu_st_floatx80_ra); +} + +uint32_t HELPER(fmovemx_st_postinc)(CPUM68KState *env, uint32_t addr, + uint32_t mask) +{ + return fmovem_postinc(env, addr, mask, cpu_st_floatx80_ra); +} + +uint32_t HELPER(fmovemx_ld_postinc)(CPUM68KState *env, uint32_t addr, + uint32_t mask) +{ + return fmovem_postinc(env, addr, mask, cpu_ld_floatx80_ra); +} + +uint32_t HELPER(fmovemd_st_predec)(CPUM68KState *env, uint32_t addr, + uint32_t mask) +{ + return fmovem_predec(env, addr, mask, cpu_st_float64_ra); +} + +uint32_t HELPER(fmovemd_st_postinc)(CPUM68KState *env, uint32_t addr, + uint32_t mask) +{ + return fmovem_postinc(env, addr, mask, cpu_st_float64_ra); +} + +uint32_t HELPER(fmovemd_ld_postinc)(CPUM68KState *env, uint32_t addr, + uint32_t mask) +{ + return fmovem_postinc(env, addr, mask, cpu_ld_float64_ra); +} diff --git a/target/m68k/helper.h b/target/m68k/helper.h index b396899..475a1f2 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -54,6 +54,12 @@ DEF_HELPER_FLAGS_3(fcmp, TCG_CALL_NO_RWG, void, env, fp,= fp) DEF_HELPER_FLAGS_2(set_fpcr, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_2(ftst, TCG_CALL_NO_RWG, void, env, fp) DEF_HELPER_3(fconst, void, env, fp, i32) +DEF_HELPER_3(fmovemx_st_predec, i32, env, i32, i32) +DEF_HELPER_3(fmovemx_st_postinc, i32, env, i32, i32) +DEF_HELPER_3(fmovemx_ld_postinc, i32, env, i32, i32) +DEF_HELPER_3(fmovemd_st_predec, i32, env, i32, i32) +DEF_HELPER_3(fmovemd_st_postinc, i32, env, i32, i32) +DEF_HELPER_3(fmovemd_ld_postinc, i32, env, i32, i32) =20 DEF_HELPER_3(mac_move, void, env, i32, i32) DEF_HELPER_3(macmulf, i64, env, i32, i32) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 89ac2c7..3a519b7 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4505,13 +4505,72 @@ static void gen_op_fmove_fcr(CPUM68KState *env, Dis= asContext *s, tcg_temp_free_i32(addr); } =20 +static void gen_op_fmovem(CPUM68KState *env, DisasContext *s, + uint32_t insn, uint32_t ext) +{ + int opsize; + TCGv addr, tmp; + int mode =3D (ext >> 11) & 0x3; + int is_load =3D ((ext & 0x2000) =3D=3D 0); + + if (m68k_feature(s->env, M68K_FEATURE_FPU)) { + opsize =3D OS_EXTENDED; + } else { + opsize =3D OS_DOUBLE; /* FIXME */ + } + + addr =3D gen_lea(env, s, insn, opsize); + if (IS_NULL_QREG(addr)) { + gen_addr_fault(s); + return; + } + + tmp =3D tcg_temp_new(); + if (mode & 0x1) { + /* Dynamic register list */ + tcg_gen_ext8u_i32(tmp, DREG(ext, 4)); + } else { + /* Static register list */ + tcg_gen_movi_i32(tmp, ext & 0xff); + } + + if (!is_load && (mode & 2) =3D=3D 0) { + /* predecrement addressing mode + * only available to store register to memory + */ + if (opsize =3D=3D OS_EXTENDED) { + gen_helper_fmovemx_st_predec(tmp, cpu_env, addr, tmp); + } else { + gen_helper_fmovemd_st_predec(tmp, cpu_env, addr, tmp); + } + } else { + /* postincrement addressing mode */ + if (opsize =3D=3D OS_EXTENDED) { + if (is_load) { + gen_helper_fmovemx_ld_postinc(tmp, cpu_env, addr, tmp); + } else { + gen_helper_fmovemx_st_postinc(tmp, cpu_env, addr, tmp); + } + } else { + if (is_load) { + gen_helper_fmovemd_ld_postinc(tmp, cpu_env, addr, tmp); + } else { + gen_helper_fmovemd_st_postinc(tmp, cpu_env, addr, tmp); + } + } + } + if ((insn & 070) =3D=3D 030 || (insn & 070) =3D=3D 040) { + tcg_gen_mov_i32(AREG(insn, 0), tmp); + } + tcg_temp_free(tmp); +} + /* ??? FP exceptions are not implemented. Most exceptions are deferred un= til immediately before the next FP instruction is executed. */ DISAS_INSN(fpu) { uint16_t ext; int opmode; - TCGv tmp32; int opsize; TCGv_ptr cpu_src, cpu_dest; =20 @@ -4548,36 +4607,10 @@ DISAS_INSN(fpu) return; case 6: /* fmovem */ case 7: - { - TCGv addr; - TCGv_ptr fp; - uint16_t mask; - int i; - if ((ext & 0x1f00) !=3D 0x1000 || (ext & 0xff) =3D=3D 0) - goto undef; - tmp32 =3D gen_lea(env, s, insn, OS_LONG); - if (IS_NULL_QREG(tmp32)) { - gen_addr_fault(s); - return; - } - addr =3D tcg_temp_new_i32(); - tcg_gen_mov_i32(addr, tmp32); - mask =3D 0x80; - fp =3D tcg_temp_new_ptr(); - for (i =3D 0; i < 8; i++) { - if (ext & mask) { - tcg_gen_addi_ptr(fp, cpu_env, - offsetof(CPUM68KState, fregs[i])); - gen_ldst_fp(s, OS_DOUBLE, addr, fp, - (ext & (1 << 13)) ? EA_STORE : EA_LOADS); - if (ext & (mask - 1)) - tcg_gen_addi_i32(addr, addr, 8); - } - mask >>=3D 1; - } - tcg_temp_free_i32(addr); - tcg_temp_free_ptr(fp); + if ((ext & 0x1000) =3D=3D 0 && !m68k_feature(s->env, M68K_FEATURE_= FPU)) { + goto undef; } + gen_op_fmovem(env, s, insn, ext); return; } if (ext & (1 << 14)) { --=20 2.9.4