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[73.207.178.95]) by smtp.gmail.com with ESMTPSA id s29sm2914542ywa.45.2017.06.29.17.41.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Jun 2017 17:41:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ldNYyXBXe4fitCOW4uZE6dsmaGLZQljtXhp0lrdSvgg=; b=R0S6Lo9afOQIk7OHUdAQSxIXReO619mAXauJiV1S2sn1oOggrmB6EeBgmR6XNWqGqX 4LkxvqWNy23uLkTG/K2N7CiKil8tMiV2aoO2iuSoh+Jncl7BiBihu8l3v1jpP7slDMg6 lsSks+/7FiSeyuSDKzulJcdelD2LS80MP3zU0QA/g6OccZHDQp9BSu4prlED0iRbt2mH R6wlkFi2wIUV3qi1rMLbl/NJB/fNxgd0L1fdG9vZwNto/P638o4vozWvPrVXbQ8+04Rh Ea5zVlDmfraXA8bqw4x719+gPpCiSkQeg9BKLBPrkEdV8f3Vyhev9A4xc53LHFLnGv5g Xuvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ldNYyXBXe4fitCOW4uZE6dsmaGLZQljtXhp0lrdSvgg=; b=LeXWmDk9GCS8XQ25PtXsvj9QjFG78uj0ELD7dl9mLZfv0KrCWpxx1hqdUWyoi/v2we 6xCzEVu4J8Olos7Et1cP1Rj8JrkysMPKwZexOdVXBfbPkXvWzLqKrJVg0pM0dceX0fzf RQnUkJPtkTFRkQoYE+DMczP3xP2ZZNz9CZNDwLVXdTr43y3+WWpliJDCHsTR5N+So46M KmYP1nqgGEx5067Yj6Cd1YBnRMU4d6rMJpahCxEQ6KEB67LgEvcCA2oY6ikgVkYtKx2j 9k7MUKc1W3sW9KrcnLvEpMsEu8zy5O21nPL3IXlgw2B63pNaM9WBG56O+ytB9OrrJOdh qvhQ== X-Gm-Message-State: AKS2vOyRMVKNzqkPWTm5QvH4//dK0yxpukhb8nGRP5xkge1igvhSqHTO bfJ5OI7awrzDgw== X-Received: by 10.129.125.4 with SMTP id y4mr454501ywc.299.1498783266088; Thu, 29 Jun 2017 17:41:06 -0700 (PDT) From: Pranith Kumar To: alex.bennee@linaro.org Date: Thu, 29 Jun 2017 20:40:59 -0400 Message-Id: <20170630004059.25619-4-bobby.prani@gmail.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170630004059.25619-1-bobby.prani@gmail.com> References: <20170630004059.25619-1-bobby.prani@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4002:c05::241 Subject: [Qemu-devel] [PATCH v3 3/3] tcg/aarch64: Enable indirect jump path using LDR (literal) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This patch enables the indirect jump path using an LDR (literal) instruction. It will be interesting to test and see which performs better among the two paths. CC: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Pranith Kumar --- tcg/aarch64/tcg-target.inc.c | 42 ++++++++++++++++++++++++++++------------= -- 1 file changed, 28 insertions(+), 14 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index f059d9d781..b0801d0259 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -269,6 +269,8 @@ typedef enum { I3207_BLR =3D 0xd63f0000, I3207_RET =3D 0xd65f0000, =20 + /* Load literal for loading the address at pc-relative offset */ + I3305_LDR =3D 0x58000000, /* Load/store register. Described here as 3.3.12, but the helper that emits them can transform to 3.3.10 or 3.3.13. */ I3312_STRB =3D 0x38000000 | LDST_ST << 22 | MO_8 << 30, @@ -389,6 +391,11 @@ static inline uint32_t tcg_in32(TCGContext *s) #define tcg_out_insn(S, FMT, OP, ...) \ glue(tcg_out_insn_,FMT)(S, glue(glue(glue(I,FMT),_),OP), ## __VA_ARGS_= _) =20 +static void tcg_out_insn_3305(TCGContext *s, AArch64Insn insn, int imm19, = TCGReg rt) +{ + tcg_out32(s, insn | (imm19 & 0x7ffff) << 5 | rt); +} + static void tcg_out_insn_3201(TCGContext *s, AArch64Insn insn, TCGType ext, TCGReg rt, int imm19) { @@ -864,6 +871,8 @@ static inline void tcg_out_call(TCGContext *s, tcg_insn= _unit *target) } } =20 +#ifdef USE_DIRECT_JUMP + void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr) { tcg_insn_unit *code_ptr =3D (tcg_insn_unit *)jmp_addr; @@ -889,6 +898,8 @@ void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uint= ptr_t addr) flush_icache_range(jmp_addr, jmp_addr + 8); } =20 +#endif + static inline void tcg_out_goto_label(TCGContext *s, TCGLabel *l) { if (!l->has_value) { @@ -1400,21 +1411,24 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_goto_tb: -#ifndef USE_DIRECT_JUMP -#error "USE_DIRECT_JUMP required for aarch64" -#endif - /* consistency for USE_DIRECT_JUMP */ - tcg_debug_assert(s->tb_jmp_insn_offset !=3D NULL); - /* Ensure that ADRP+ADD are 8-byte aligned so that an atomic - write can be used to patch the target address. */ - if ((uintptr_t)s->code_ptr & 7) { - tcg_out32(s, NOP); + if (s->tb_jmp_insn_offset !=3D NULL) { + /* USE_DIRECT_JUMP */ + /* Ensure that ADRP+ADD are 8-byte aligned so that an atomic + write can be used to patch the target address. */ + if ((uintptr_t)s->code_ptr & 7) { + tcg_out32(s, NOP); + } + s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); + /* actual branch destination will be patched by + aarch64_tb_set_jmp_target later. */ + tcg_out_insn(s, 3406, ADRP, TCG_REG_TMP, 0); + tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_TMP, TCG_REG= _TMP, 0); + } else { + /* !USE_DIRECT_JUMP */ + tcg_debug_assert(s->tb_jmp_target_addr !=3D NULL); + intptr_t offset =3D tcg_pcrel_diff(s, (s->tb_jmp_target_addr += a0)) >> 2; + tcg_out_insn(s, 3305, LDR, offset, TCG_REG_TMP); } - s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); - /* actual branch destination will be patched by - aarch64_tb_set_jmp_target later. */ - tcg_out_insn(s, 3406, ADRP, TCG_REG_TMP, 0); - tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_TMP, TCG_REG_TMP= , 0); tcg_out_insn(s, 3207, BR, TCG_REG_TMP); s->tb_jmp_reset_offset[a0] =3D tcg_current_code_size(s); break; --=20 2.13.0