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[97.113.165.157]) by smtp.gmail.com with ESMTPSA id g10sm1589117pgr.18.2017.06.15.22.15.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Jun 2017 22:15:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=1ULMzzvxq3aVEX8mxhkIxndITtGcQyB/e7zS8GhUP6o=; b=lYB0Wx9YVNyaUJC/W2R4VpLXvKMxC0LLdDlx76GGsj7eo13ZEcpV+VOPBXNt1w5DpV +Ph+70CZe4lRj9eW1JYwbDjzArDZdM1BkT8bg+G82Wreb6+l6oe/Jwk6MGYomfU9BSQ/ MDehLPVH/wEUHtame8fqgQ3tHI5q5q7erqFo/+Em6hOCWBRH3UKBoy9BhA0Gx7ZO99UK C6s2FuT6/C1CQzoSBiFiNAHCr9eMuXWxAk/ZEzxG29hNmrQf6Lo/Sqgdwx0aixMApluU ZULXASx7mPg1ThfYf5yyUnECvD2LjcZrR0Je66WaNFas6kz8w5kb30En2qTJRf1svnG8 dPUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=1ULMzzvxq3aVEX8mxhkIxndITtGcQyB/e7zS8GhUP6o=; b=WcC/LdpSvXDl9vKY+hbOSPo2G1RVDKK6Ovk0MkzeeerUC0+d6Ajcv3fkUeitoLYuc5 2SdFiuwRLZcYTkQRY5jMelHfOw68AeeKED/IW/y4hJchYv2dQPpPQoVjqed+ufqpWxPv D/JEDR36UiIE7ahHRjscZP7FpP1b3rTlRRL50/D/PI1SE/dRd0Istu24TO5FtxvMVvz0 h+kelqVXQnA9bbGlA3G1r4f4KJ1LcSBIs9ZGuY9K+/5/l2m+su2JiLeTNkBKaP9cYnk7 WvTLXuxcDKeszZ3//D92KRvMmfksILdLHiolemxVsqz00tTBGGf8owipYuw8O/cKbYJl YDJg== X-Gm-Message-State: AKS2vOxuwVr6q2HuMsSfhc7mP2i+OfYie8hTLLBDp0D4Nm5P5zv6vXfu VwbP7QHkfsYcH+MXf44= X-Received: by 10.84.238.137 with SMTP id v9mr10740859plk.154.1497590128926; Thu, 15 Jun 2017 22:15:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 15 Jun 2017 22:15:26 -0700 Message-Id: <20170616051526.6814-1-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v2] target/s390x: Enforce instruction features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Introduce a synthetic feature (type MISC) to handle disabling of the enforcing of features at translation time. Signed-off-by: Richard Henderson --- target/s390x/cpu_features.c | 4 +++- target/s390x/cpu_features_def.h | 1 + target/s390x/cpu_models.c | 5 +++++ target/s390x/translate.c | 9 +++++++++ 4 files changed, 18 insertions(+), 1 deletion(-) diff --git a/target/s390x/cpu_features.c b/target/s390x/cpu_features.c index 42fd9d7..8d542c0 100644 --- a/target/s390x/cpu_features.c +++ b/target/s390x/cpu_features.c @@ -24,7 +24,7 @@ } =20 /* indexed by feature number for easy lookup */ -static const S390FeatDef s390_features[] =3D { +static const S390FeatDef s390_features[S390_FEAT_MAX] =3D { FEAT_INIT("esan3", S390_FEAT_TYPE_STFL, 0, "Instructions marked as n3"= ), FEAT_INIT("zarch", S390_FEAT_TYPE_STFL, 1, "z/Architecture architectur= al mode"), FEAT_INIT("dateh", S390_FEAT_TYPE_STFL, 3, "DAT-enhancement facility"), @@ -251,6 +251,8 @@ static const S390FeatDef s390_features[] =3D { FEAT_INIT("pcc-xts-eaes-256", S390_FEAT_TYPE_PCC, 60, "PCC Compute-XTS= -Parameter-Using-Encrypted-AES-256"), =20 FEAT_INIT("ppno-sha-512-drng", S390_FEAT_TYPE_PPNO, 3, "PPNO SHA-512-D= RNG"), + + FEAT_INIT("tcg-all-insns", S390_FEAT_TYPE_MISC, 0, "Enable all insns s= upported by TCG"), }; =20 const S390FeatDef *s390_feat_def(S390Feat feat) diff --git a/target/s390x/cpu_features_def.h b/target/s390x/cpu_features_de= f.h index aa5ab8d..0726c54 100644 --- a/target/s390x/cpu_features_def.h +++ b/target/s390x/cpu_features_def.h @@ -225,6 +225,7 @@ typedef enum { S390_FEAT_PCC_XTS_EAES_128, S390_FEAT_PCC_XTS_EAES_256, S390_FEAT_PPNO_SHA_512_DRNG, + S390_FEAT_TCG_ALL_INSNS, S390_FEAT_MAX, } S390Feat; =20 diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c index 478bcc6..641552e 100644 --- a/target/s390x/cpu_models.c +++ b/target/s390x/cpu_models.c @@ -685,6 +685,11 @@ static void add_qemu_cpu_model_features(S390FeatBitmap= fbm) S390_FEAT_GENERAL_INSTRUCTIONS_EXT, S390_FEAT_EXECUTE_EXT, S390_FEAT_STFLE_45, + + /* There are other features that are only partially implemented. + We do not advertise those above. Indicate that we should not + enforce PGM_OPERATION for insns without the feature bit set. */ + S390_FEAT_TCG_ALL_INSNS, }; int i; =20 diff --git a/target/s390x/translate.c b/target/s390x/translate.c index af18ffb..69c1f94 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -55,6 +55,7 @@ typedef struct DisasFields DisasFields; =20 struct DisasContext { struct TranslationBlock *tb; + const unsigned long *features; const DisasInsn *insn; DisasFields *fields; uint64_t ex_value; @@ -5600,6 +5601,12 @@ static ExitStatus translate_one(CPUS390XState *env, = DisasContext *s) } #endif =20 + /* Check for insn feature enabled. */ + if (s->features && !test_bit(insn->fac, s->features)) { + gen_program_exception(s, PGM_OPERATION); + return EXIT_NORETURN; + } + /* Check for insn specification exceptions. */ if (insn->spec) { int spec =3D insn->spec, excp =3D 0, r; @@ -5726,6 +5733,8 @@ void gen_intermediate_code(CPUS390XState *env, struct= TranslationBlock *tb) } =20 dc.tb =3D tb; + dc.features =3D (s390_has_feat(S390_FEAT_TCG_ALL_INSNS) + ? NULL : cpu->model->features); dc.pc =3D pc_start; dc.cc_op =3D CC_OP_DYNAMIC; dc.ex_value =3D tb->cs_base; --=20 2.9.4