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[97.113.165.157]) by smtp.gmail.com with ESMTPSA id k73sm310058pge.13.2017.06.14.22.54.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Jun 2017 22:54:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=vE0prwhmjj3n4qcKyXq8r1YUAsMFV72v0dxFVO6IfMY=; b=DJDPle+mHBGJB5q9yMBQdvkITP2HZ5trwcxwDVx2A6mH1QE2f5xp3RO7xIkoI0NVzr jaZ5XwCwL65VWQzmKOFO1D3nS441IRV9/rC832GgqenerfINC0rhFjOX2j6tzW8pN739 dxIUA7Gk9EPQxB/vQWSPHiJN3XYL1RVYAYdEAEyQTm6pn6GSmU4Krqd4yaJBQkK3Ot7u ollyE0cDriu/NoyeLkM5N5XqNdSGHLWVjU1nnnrQVZfniL/BjnsPaYN+Ww9faH58Ed3f kAH83cqP/TK74emmZjT3txxO+xX4stnm2aZUuQwWW6U0RO8y/Vy2MJCaGMufivf1pnH1 AXXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=vE0prwhmjj3n4qcKyXq8r1YUAsMFV72v0dxFVO6IfMY=; b=QsdbaG2gAD/0kahnJsU3xopQvQOdXYLJ0UOX5qX+LDNWtfG7K8QJ/n7SzJaOAOw3CE x/b540aISVSAjXlXTHft7rRUiuLCZj5cX4ZjrDvKbGMXmjjkQM8sSJouc5vxfAMPMnnD pNxRL4rsYPt0nD0TgigT82YPnWjW9q2NNiBA6xToPVVNT7GlObtqiA9SUMqisP8nv1HO Oe7bIA4OxcbTVqY2axNJvc8sVXxVgJAYtx/+D+VmgG1ZvY2iQFLX2X85PWuAEwqJ0SjE au5weL42IwIxF/jOOnHJQTyo361kyyjHSg4muVOZjjKi2FyxRuMUcQSdrE5eiDWdjzDb V0sg== X-Gm-Message-State: AKS2vOz8tOTl/qv3vrsSBCxuuEpj3fEX7dMCbS0uTEhiMLni5QPQQ/sF kxtVgaRj/GkhjlZN5DI= X-Received: by 10.98.142.17 with SMTP id k17mr3528284pfe.139.1497506043963; Wed, 14 Jun 2017 22:54:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 14 Jun 2017 22:53:55 -0700 Message-Id: <20170615055356.20684-5-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170615055356.20684-1-rth@twiddle.net> References: <20170615055356.20684-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH 4/5] target/s390x: implement mvcos instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: David Hildenbrand This adds support for the MOVE WITH OPTIONAL SPECIFICATIONS (MVCOS) instruction. Allow to enable it for the qemu cpu model using qemu-system-s390x ... -cpu qemu,mvcos=3Don ... This allows to boot linux kernel that uses it for uacccess. We are missing (as for most other part) low address protection checks, PSW key / storage key checks and support for AR-mode. We fake an ADDRESSING exception when called from problem state (which seems to rely on PSW key checks to be in place) and if AR-mode is used. user mode will always see a PRIVILEDGED exception. This patch is based on an original patch by Miroslav Benes (thanks!). Signed-off-by: David Hildenbrand Message-Id: <20170614133819.18480-3-david@redhat.com> Signed-off-by: Richard Henderson --- target/s390x/cpu.h | 22 +++++- target/s390x/cpu_models.c | 1 + target/s390x/helper.h | 1 + target/s390x/insn-data.def | 2 + target/s390x/mem_helper.c | 181 +++++++++++++++++++++++++++++++++++++++++= ---- target/s390x/translate.c | 9 +++ 6 files changed, 201 insertions(+), 15 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 532a4a0..5b94ace 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -304,6 +304,7 @@ void s390x_cpu_debug_excp_handler(CPUState *cs); #undef PSW_MASK_WAIT #undef PSW_MASK_PSTATE #undef PSW_MASK_ASC +#undef PSW_SHIFT_ASC #undef PSW_MASK_CC #undef PSW_MASK_PM #undef PSW_MASK_64 @@ -320,6 +321,7 @@ void s390x_cpu_debug_excp_handler(CPUState *cs); #define PSW_MASK_WAIT 0x0002000000000000ULL #define PSW_MASK_PSTATE 0x0001000000000000ULL #define PSW_MASK_ASC 0x0000C00000000000ULL +#define PSW_SHIFT_ASC 46 #define PSW_MASK_CC 0x0000300000000000ULL #define PSW_MASK_PM 0x00000F0000000000ULL #define PSW_MASK_64 0x0000000100000000ULL @@ -336,6 +338,12 @@ void s390x_cpu_debug_excp_handler(CPUState *cs); #define PSW_ASC_SECONDARY 0x0000800000000000ULL #define PSW_ASC_HOME 0x0000C00000000000ULL =20 +/* the address space values shifted */ +#define AS_PRIMARY 0 +#define AS_ACCREG 1 +#define AS_SECONDARY 2 +#define AS_HOME 3 + /* tb flags */ =20 #define FLAG_MASK_PER (PSW_MASK_PER >> 32) @@ -354,6 +362,7 @@ void s390x_cpu_debug_excp_handler(CPUState *cs); =20 /* Control register 0 bits */ #define CR0_LOWPROT 0x0000000010000000ULL +#define CR0_SECONDARY 0x0000000004000000ULL #define CR0_EDAT 0x0000000000800000ULL =20 /* MMU */ @@ -361,7 +370,18 @@ void s390x_cpu_debug_excp_handler(CPUState *cs); #define MMU_SECONDARY_IDX 1 #define MMU_HOME_IDX 2 =20 -static inline int cpu_mmu_index (CPUS390XState *env, bool ifetch) +static inline bool psw_key_valid(CPUS390XState *env, uint8_t psw_key) +{ + uint16_t pkm =3D env->cregs[3] >> 16; + + if (env->psw.mask & PSW_MASK_PSTATE) { + /* PSW key has range 0..15, it is valid if the bit is 1 in the PKM= */ + return pkm & (0x80 >> psw_key); + } + return true; +} + +static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) { switch (env->psw.mask & PSW_MASK_ASC) { case PSW_ASC_PRIMARY: diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c index 478bcc6..c3a4ce6 100644 --- a/target/s390x/cpu_models.c +++ b/target/s390x/cpu_models.c @@ -682,6 +682,7 @@ static void add_qemu_cpu_model_features(S390FeatBitmap = fbm) S390_FEAT_LONG_DISPLACEMENT_FAST, S390_FEAT_ETF2_ENH, S390_FEAT_STORE_CLOCK_FAST, + S390_FEAT_MOVE_WITH_OPTIONAL_SPEC, S390_FEAT_GENERAL_INSTRUCTIONS_EXT, S390_FEAT_EXECUTE_EXT, S390_FEAT_STFLE_45, diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 69249a5..b268367 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -105,6 +105,7 @@ DEF_HELPER_FLAGS_1(stfl, TCG_CALL_NO_RWG, void, env) DEF_HELPER_2(stfle, i32, env, i64) DEF_HELPER_FLAGS_2(lpq, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_4(stpq, TCG_CALL_NO_WG, void, env, i64, i64, i64) +DEF_HELPER_4(mvcos, i32, env, i64, i64, i64) =20 #ifndef CONFIG_USER_ONLY DEF_HELPER_3(servc, i32, env, i64, i64) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index d089707..aa4c5b2 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -590,6 +590,8 @@ C(0xb254, MVPG, RRE, Z, r1_o, r2_o, 0, 0, mvpg, 0) /* MOVE STRING */ C(0xb255, MVST, RRE, Z, r1_o, r2_o, 0, 0, mvst, 0) +/* MOVE WITH OPTIONAL SPECIFICATION */ + C(0xc800, MVCOS, SSF, MVCOS, la1, a2, 0, 0, mvcos, 0) /* MOVE WITH OFFSET */ /* Really format SS_b, but we pack both lengths into one argument for the helper call, so we might as well leave one 8-bit field. */ diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 80caab9..6125725 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -110,6 +110,20 @@ static inline void cpu_stsize_data_ra(CPUS390XState *e= nv, uint64_t addr, } } =20 +static inline uint64_t wrap_address(CPUS390XState *env, uint64_t a) +{ + if (!(env->psw.mask & PSW_MASK_64)) { + if (!(env->psw.mask & PSW_MASK_32)) { + /* 24-Bit mode */ + a &=3D 0x00ffffff; + } else { + /* 31-Bit mode */ + a &=3D 0x7fffffff; + } + } + return a; +} + static void fast_memset(CPUS390XState *env, uint64_t dest, uint8_t byte, uint32_t l, uintptr_t ra) { @@ -133,6 +147,68 @@ static void fast_memset(CPUS390XState *env, uint64_t d= est, uint8_t byte, } } =20 +#ifndef CONFIG_USER_ONLY +static void fast_memmove_idx(CPUS390XState *env, uint64_t dest, uint64_t s= rc, + uint32_t len, int dest_idx, int src_idx, + uintptr_t ra) +{ + TCGMemOpIdx oi_dest =3D make_memop_idx(MO_UB, dest_idx); + TCGMemOpIdx oi_src =3D make_memop_idx(MO_UB, src_idx); + uint32_t len_adj; + void *src_p; + void *dest_p; + uint8_t x; + + while (len > 0) { + src =3D wrap_address(env, src); + dest =3D wrap_address(env, dest); + src_p =3D tlb_vaddr_to_host(env, src, MMU_DATA_LOAD, src_idx); + dest_p =3D tlb_vaddr_to_host(env, dest, MMU_DATA_STORE, dest_idx); + + if (src_p && dest_p) { + /* Access to both whole pages granted. */ + len_adj =3D adj_len_to_page(adj_len_to_page(len, src), dest); + memmove(dest_p, src_p, len_adj); + } else { + /* We failed to get access to one or both whole pages. The next + read or write access will likely fill the QEMU TLB for the + next iteration. */ + len_adj =3D 1; + x =3D helper_ret_ldub_mmu(env, src, oi_src, ra); + helper_ret_stb_mmu(env, dest, x, oi_dest, ra); + } + src +=3D len_adj; + dest +=3D len_adj; + len -=3D len_adj; + } +} + +static int mmu_idx_from_as(uint8_t as) +{ + switch (as) { + case AS_PRIMARY: + return MMU_PRIMARY_IDX; + case AS_SECONDARY: + return MMU_SECONDARY_IDX; + case AS_HOME: + return MMU_HOME_IDX; + default: + /* FIXME AS_ACCREG */ + g_assert_not_reached(); + } +} + +static void fast_memmove_as(CPUS390XState *env, uint64_t dest, uint64_t sr= c, + uint32_t len, uint8_t dest_as, uint8_t src_as, + uintptr_t ra) +{ + int src_idx =3D mmu_idx_from_as(src_as); + int dest_idx =3D mmu_idx_from_as(dest_as); + + fast_memmove_idx(env, dest, src, len, dest_idx, src_idx, ra); +} +#endif + static void fast_memmove(CPUS390XState *env, uint64_t dest, uint64_t src, uint32_t l, uintptr_t ra) { @@ -408,20 +484,6 @@ uint32_t HELPER(clm)(CPUS390XState *env, uint32_t r1, = uint32_t mask, return cc; } =20 -static inline uint64_t wrap_address(CPUS390XState *env, uint64_t a) -{ - if (!(env->psw.mask & PSW_MASK_64)) { - if (!(env->psw.mask & PSW_MASK_32)) { - /* 24-Bit mode */ - a &=3D 0x00ffffff; - } else { - /* 31-Bit mode */ - a &=3D 0x7fffffff; - } - } - return a; -} - static inline uint64_t get_address(CPUS390XState *env, int reg) { return wrap_address(env, env->regs[reg]); @@ -1789,3 +1851,94 @@ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, u= int64_t r1, uint64_t addr) that requires such execution. */ env->ex_value =3D insn | ilen; } + +uint32_t HELPER(mvcos)(CPUS390XState *env, uint64_t dest, uint64_t src, + uint64_t len) +{ + const uint8_t psw_key =3D (env->psw.mask & PSW_MASK_KEY) >> PSW_SHIFT_= KEY; + const uint8_t psw_as =3D (env->psw.mask & PSW_MASK_ASC) >> PSW_SHIFT_A= SC; + const uint64_t r0 =3D env->regs[0]; + const uintptr_t ra =3D GETPC(); + CPUState *cs =3D CPU(s390_env_get_cpu(env)); + uint8_t dest_key, dest_as, dest_k, dest_a; + uint8_t src_key, src_as, src_k, src_a; + uint64_t val; + int cc =3D 0; + + HELPER_LOG("%s dest %" PRIx64 ", src %" PRIx64 ", len %" PRIx64 "\n", + __func__, dest, src, len); + + if (!(env->psw.mask & PSW_MASK_DAT)) { + cpu_restore_state(cs, ra); + program_interrupt(env, PGM_SPECIAL_OP, 6); + } + + /* OAC (operand access control) for the first operand -> dest */ + val =3D (r0 & 0xffff0000ULL) >> 16; + dest_key =3D (val >> 12) & 0xf; + dest_as =3D (val >> 6) & 0x3; + dest_k =3D (val >> 1) & 0x1; + dest_a =3D val & 0x1; + + /* OAC (operand access control) for the second operand -> src */ + val =3D (r0 & 0x0000ffffULL); + src_key =3D (val >> 12) & 0xf; + src_as =3D (val >> 6) & 0x3; + src_k =3D (val >> 1) & 0x1; + src_a =3D val & 0x1; + + if (!dest_k) { + dest_key =3D psw_key; + } + if (!src_k) { + src_key =3D psw_key; + } + if (!dest_a) { + dest_as =3D psw_as; + } + if (!src_a) { + src_as =3D psw_as; + } + + if (dest_a && dest_as =3D=3D AS_HOME && (env->psw.mask & PSW_MASK_PSTA= TE)) { + cpu_restore_state(cs, ra); + program_interrupt(env, PGM_SPECIAL_OP, 6); + } + if (!(env->cregs[0] & CR0_SECONDARY) && + (dest_as =3D=3D AS_SECONDARY || src_as =3D=3D AS_SECONDARY)) { + cpu_restore_state(cs, ra); + program_interrupt(env, PGM_SPECIAL_OP, 6); + } + if (!psw_key_valid(env, dest_key) || !psw_key_valid(env, src_key)) { + cpu_restore_state(cs, ra); + program_interrupt(env, PGM_PRIVILEGED, 6); + } + + len =3D wrap_length(env, len); + if (len > 4096) { + cc =3D 3; + len =3D 4096; + } + + /* FIXME: AR-mode and proper problem state mode (using PSW keys) missi= ng */ + if (src_as =3D=3D AS_ACCREG || dest_as =3D=3D AS_ACCREG || + (env->psw.mask & PSW_MASK_PSTATE)) { + qemu_log_mask(LOG_UNIMP, "%s: AR-mode and PSTATE support missing\n= ", + __func__); + cpu_restore_state(cs, ra); + program_interrupt(env, PGM_ADDRESSING, 6); + } + + /* FIXME: a) LAP + * b) Access using correct keys + * c) AR-mode + */ +#ifdef CONFIG_USER_ONLY + /* psw keys are never valid in user mode, we will never reach this */ + g_assert_not_reached(); +#else + fast_memmove_as(env, dest, src, len, dest_as, src_as, ra); +#endif + + return cc; +} diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 4773a10..a546119 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -3040,6 +3040,14 @@ static ExitStatus op_mvclu(DisasContext *s, DisasOps= *o) return NO_EXIT; } =20 +static ExitStatus op_mvcos(DisasContext *s, DisasOps *o) +{ + int r3 =3D get_field(s->fields, r3); + gen_helper_mvcos(cc_op, cpu_env, o->addr1, o->in2, regs[r3]); + set_cc_static(s); + return NO_EXIT; +} + #ifndef CONFIG_USER_ONLY static ExitStatus op_mvcp(DisasContext *s, DisasOps *o) { @@ -5409,6 +5417,7 @@ enum DisasInsnEnum { #define FAC_SCF S390_FEAT_STORE_CLOCK_FAST #define FAC_SFLE S390_FEAT_STFLE #define FAC_ILA S390_FEAT_STFLE_45 /* interlocked-access-facility = 1 */ +#define FAC_MVCOS S390_FEAT_MOVE_WITH_OPTIONAL_SPEC #define FAC_LPP S390_FEAT_SET_PROGRAM_PARAMETERS /* load-program-p= arameter */ #define FAC_DAT_ENH S390_FEAT_DAT_ENH #define FAC_E2 S390_FEAT_EXTENDED_TRANSLATION_2 --=20 2.9.4