From nobody Wed Nov 5 13:50:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1497472502680586.7484839377752; Wed, 14 Jun 2017 13:35:02 -0700 (PDT) Received: from localhost ([::1]:50735 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dLF0G-0004qD-BS for importer@patchew.org; Wed, 14 Jun 2017 16:35:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35340) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dLEz8-0004G1-0c for qemu-devel@nongnu.org; Wed, 14 Jun 2017 16:33:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dLEz6-0006yR-Vg for qemu-devel@nongnu.org; Wed, 14 Jun 2017 16:33:50 -0400 Received: from out4-smtp.messagingengine.com ([66.111.4.28]:41163) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dLEz2-0006xm-Du; Wed, 14 Jun 2017 16:33:44 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 1DF0F20CFF; Wed, 14 Jun 2017 16:33:44 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 14 Jun 2017 16:33:44 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id D700F249CD; Wed, 14 Jun 2017 16:33:43 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=hpP1ds6EZfmJ5Tc fFEzajWxyavCIjFS9MAUJGRraDQQ=; b=G9bmdJnw72jvxqzu75aWQ9U4gLRZ9uq /krrxfFnilU9eUOGXqyM85gdJNp6D1K/bcWbJuzr1Ycev5CZf8ZKWM7T8tln+C19 Bx0VRYO9A0mi4SuIzBogcbJadWaAZfje0ONq5n97DNNS5deTJ9ksLaDPg3xZVibh haFe4sVLTkhk= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=hpP1ds6EZfmJ5TcfFEzajWxyavCIjFS9MAUJGRraDQQ=; b=JAIZkl4z miyrVgJ7N7jGWtWIDQ1qfZ+0wYbwSTtmo00+AbfRSIJJkEKatRJVmZvEF6SLjoig Q9WZHjsa0BonQKGEPWIj09nbH0jUNhISPYLVV7j9k0s506oKL1aLUJmSu+oBiTVc z3kCEhtgSjrYKw+rm+kmQbTePuBpwgvv8nA/Qo0sK28LLheGex8FVbqpqL5SyDeQ Z/B7NEhYNpPDIYeaiqsIZ7YycvQW3ravAcHIEc/Zz/GjPQTUTjT7LAU6sKzt4rIg 6t7CWyB+tlCMUhNWihcW+4stsIGJqhHFQ85TwZU2vu1VeBqvmyJKpyZrmZg144mF 2Jbp7AqO2adUww== X-ME-Sender: X-Sasl-enc: SSTxajjbPbqXLSIhfJHd2tlEs94Qu8iIBxQ7UHZtb4V+ 1497472423 Date: Wed, 14 Jun 2017 16:33:43 -0400 From: "Emilio G. Cota" To: Richard Henderson Message-ID: <20170614203343.GB8420@flamenco> References: <20170614194821.8754-1-rth@twiddle.net> <20170614194821.8754-6-rth@twiddle.net> MIME-Version: 1.0 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <20170614194821.8754-6-rth@twiddle.net> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.28 Subject: [Qemu-devel] [PATCH] target/aarch64: exit to main loop after 'msr daifclr' X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, qemu-arm@nongnu.org, alex.bennee@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On Wed, Jun 14, 2017 at 12:48:21 -0700, Richard Henderson wrote: > Exit to cpu loop so we reevaluate cpu_arm_hw_interrupts. >=20 > Cc: qemu-arm@nongnu.org > Cc: Peter Maydell > Signed-off-by: Richard Henderson > --- > target/arm/translate-a64.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) >=20 > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 860e279..e55547d 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -1422,7 +1422,9 @@ static void handle_msr_i(DisasContext *s, uint32_t = insn, > gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm); > tcg_temp_free_i32(tcg_imm); > tcg_temp_free_i32(tcg_op); > - s->is_jmp =3D DISAS_UPDATE; > + /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs.= */ > + gen_a64_set_pc_im(s->pc); For op !=3D 0x1f we end up setting the pc twice (first here, then in the switch statement). It's still correct though. > + s->is_jmp =3D (op =3D=3D 0x1f ? DISAS_EXIT : DISAS_JUMP); Could do without the parens. > break; > } > default: > @@ -11369,6 +11371,9 @@ void gen_intermediate_code_a64(ARMCPU *cpu, Trans= lationBlock *tb) > case DISAS_JUMP: > tcg_gen_lookup_and_goto_ptr(cpu_pc); > break; > + case DISAS_EXIT: > + tcg_gen_exit_tb(0); > + break; We could also mention the regression in the commit log. In fact I just did that :-) feel free to reuse parts of the below. Thanks, E. Reviewed-by: Emilio G. Cota Tested-by: Emilio G. Cota --- 8< --- Commit e75449a3 ("target/aarch64: optimize indirect branches") causes a regression by which -smp > 1 freezes under TCG, even with `-accel accel=3Dtcg,thread=3Dsingle' (i.e. MTTCG disabled). The cause of the regression is well described here by Alex: On Wed, Jun 14, 2017 at 15:02:06 +0100, Alex Benn=C3=A9e wrote: > Fundamentally the problem was that an interrupt was pending > (interrupt_request was set) but the "msr daifclr" operations when the > kernel did local_irq/fiq_enable() never got handled because the > cpu_idle loop was being very efficiently chained. As a result we never > got around to exiting the TCG code and calling arm_cpu_do_interrupt > which would then raise the IRQ to move things on > [ Message-Id: <20170614140209.29847-1-alex.bennee@linaro.org> ] Fix it by enforcing an exit to the main loop right after 'msr daifclr' is executed. Signed-off-by: Emilio G. Cota --- target/arm/translate-a64.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 860e279..323e419 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1422,7 +1422,8 @@ static void handle_msr_i(DisasContext *s, uint32_t in= sn, gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm); tcg_temp_free_i32(tcg_imm); tcg_temp_free_i32(tcg_op); - s->is_jmp =3D DISAS_UPDATE; + /* force exit to the main loop for DAIFClear */ + s->is_jmp =3D op =3D=3D 0x1f ? DISAS_EXIT : DISAS_UPDATE; break; } default: @@ -11362,6 +11363,10 @@ void gen_intermediate_code_a64(ARMCPU *cpu, Transl= ationBlock *tb) case DISAS_NEXT: gen_goto_tb(dc, 1, dc->pc); break; + case DISAS_EXIT: + gen_a64_set_pc_im(dc->pc); + tcg_gen_exit_tb(0); + break; default: case DISAS_UPDATE: gen_a64_set_pc_im(dc->pc); --=20 2.7.4