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[97.113.165.157]) by smtp.gmail.com with ESMTPSA id j65sm9528787qkf.38.2017.06.13.13.27.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 13 Jun 2017 13:27:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=h/TlhAxpS0unkw8gJJTKPoJMV/b4BT5V7/xlK1/TmK0=; b=TMpL9kX/WrSM2Ef9kzL3x0WVk5d7+ZVs7xG42wKtLTW/kqv9efQGrG9AYo4vvqdV3z WG+zEBRHC6Gt+wT7lNUTofBNnTajUKC1opc8KTZnBZaMWL4Fp5nL5LcTKw0xM3dALM2Y x+2NNNS4QStMl58ti3v/SlDgRqUtw2emKDBT1KP1UJmvfuwNfR0J/B0EArcV2zFrUOWh m7J6jtLthnppOjQkm81T5qOKbCbERIlfGeM3+VcRPtIsto9EUTuw/fzModN40PfNdK6U 8sfKZ54TBdkTQ/wnCUfT390VgiSCX64qVUNNhJwD7A+TMVpYw4oO50VibRobgSfkGnQw 4cJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=h/TlhAxpS0unkw8gJJTKPoJMV/b4BT5V7/xlK1/TmK0=; b=NXX2fRCEX8kfFx98Zdx1cvAh4HlbApYc/QOW3zt4ixAzvxajA4J7lICQi9M+Vp+Fr4 c9OeCiKoBN/qiR/pxbo4maDY7PAGhwfp7uPzFtRdAyCKWtfy6uyPsrDEvy5jpI4zKpG4 m48g4XuwzEOO3dJvZOu5+yWtiNJckFUmPdV0Rz4ZPkuw/TGpLINw7jsesjxWY1ewAcsu vFUzlIH2y4OzaxAsXtnRWXmhmtK/8+rFG9zErEa8hfy/qoYaAAjPDls4UZMd6opo9MJW iE/9V0jktgRd5RPos1F4JqkFTIxBKx/AwZ7SkfLqVLNJ/g7LGE2/KkK6GjNinbXJ+5Yw hf2A== X-Gm-Message-State: AKS2vOyCXcq8OqfXyicK+osc9igB6ErjzTLNpBmGKCZFeupwVmLsHE6J NcX7osiZrfpapSTmqm4= X-Received: by 10.55.170.202 with SMTP id t193mr2347927qke.190.1497385626073; Tue, 13 Jun 2017 13:27:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 13 Jun 2017 13:26:57 -0700 Message-Id: <20170613202659.1920-2-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170613202659.1920-1-rth@twiddle.net> References: <20170613202659.1920-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::241 Subject: [Qemu-devel] [PULL 1/3] target/s390x: correctly indicate PER nullification X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, David Hildenbrand Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: David Hildenbrand Signed-off-by: David Hildenbrand Message-Id: <20170609142156.18767-2-david@redhat.com> Signed-off-by: Richard Henderson --- target/s390x/misc_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c index edcdf17..d6eda83 100644 --- a/target/s390x/misc_helper.c +++ b/target/s390x/misc_helper.c @@ -668,6 +668,7 @@ void HELPER(per_ifetch)(CPUS390XState *env, uint64_t ad= dr) if (env->cregs[9] & PER_CR9_EVENT_NULLIFICATION) { CPUState *cs =3D CPU(s390_env_get_cpu(env)); =20 + env->per_perc_atmid |=3D PER_CODE_EVENT_NULLIFICATION; env->int_pgm_code =3D PGM_PER; env->int_pgm_ilen =3D get_ilen(cpu_ldub_code(env, addr)); =20 --=20 2.9.4 From nobody Sat Feb 7 06:50:17 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1497386435432940.2113921559286; Tue, 13 Jun 2017 13:40:35 -0700 (PDT) Received: from localhost ([::1]:45141 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKsc6-0006Wh-5e for importer@patchew.org; Tue, 13 Jun 2017 16:40:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40012) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKsP8-00037H-BL for qemu-devel@nongnu.org; Tue, 13 Jun 2017 16:27:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dKsP6-00043T-AW for qemu-devel@nongnu.org; Tue, 13 Jun 2017 16:27:10 -0400 Received: from mail-qt0-x241.google.com ([2607:f8b0:400d:c0d::241]:34905) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dKsP6-00043N-5A for qemu-devel@nongnu.org; Tue, 13 Jun 2017 16:27:08 -0400 Received: by mail-qt0-x241.google.com with SMTP id x58so37622262qtc.2 for ; Tue, 13 Jun 2017 13:27:08 -0700 (PDT) Received: from bigtime.twiddle.net.com (97-113-165-157.tukw.qwest.net. [97.113.165.157]) by smtp.gmail.com with ESMTPSA id j65sm9528787qkf.38.2017.06.13.13.27.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 13 Jun 2017 13:27:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ippe5JfYgpv4HkXcD+fEjE8TcALO1Jh/mdmoWSgQLc4=; b=JCraKxlU2SUbL+L98Jq9+3tfYySY9cXjvivoR8q6/zTvq9XqIelFbPn+E4Ze2UlJSs 8RPSigQNLnMuho457fBmYThPSrFwS8O7pWjtYDuORzEIrPCbjIu1eFcwd7ugmDaLxgYY wykNC3YmFh5sm4RgXhmzl5z2GVox+gUknAoYeEpWma7X2vebE56FJbzF++y1p1fqMc+K 3qGRDeVY/yQE7taGxsSr0X/qaIdidzb0I/hOTOmiioEd4pGXMADFTnfjb0MjxpcFd5Iy sF+AuK47Y0qAXCw+xkfu2rkxKO9K9xBZEFgIw29HwHaLfO3CMU6Z+s5Obe0g5bAiKl26 l0tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=Ippe5JfYgpv4HkXcD+fEjE8TcALO1Jh/mdmoWSgQLc4=; b=AdO/AbMIYhNSTk4z89E+MYoqCnoich/LJ8CYpAlTF7CTcWAPkNxVSOMXDWYFAbOk0m 4m0Gf06EoLl/s5hE6F1uNx/l2ZBmdFxZEmuQ+MpsZLjPr3ley3GR/NAEMjhbfvwCKtkv RbqcPrTUKWRNi3alp6BYqwwPMw9z31yYVEt6tdQGLuKBpStQ+I37QSheaHgWQtwek2TN DH5NOhwcxo+goCA+d4CMRZMCKUmTqpUVDbfxDJyc7aoMhyx6RMS0+EYfTgPJhJ9JqHsk 5QekM23vYfd38GAObvfrWFJYWid/EPLCy/sGdFKoWgVm5Exy0XqJJ3jmMP6itUvsQgtQ KJAA== X-Gm-Message-State: AKS2vOz9C5aMtF5j0gHTbHW2sFHubzxNh3ej7wzvClXSV7GIB80DzKOA uHkM4DIr8br7z2NNXxw= X-Received: by 10.55.181.69 with SMTP id e66mr2005029qkf.109.1497385627349; Tue, 13 Jun 2017 13:27:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 13 Jun 2017 13:26:58 -0700 Message-Id: <20170613202659.1920-3-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170613202659.1920-1-rth@twiddle.net> References: <20170613202659.1920-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::241 Subject: [Qemu-devel] [PULL 2/3] target/s390x: rework PGM interrupt psw.addr handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, David Hildenbrand Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: David Hildenbrand We can tell from the program interrupt code, whether a program interrupt has to forward the address in the PGM new PSW (suppressing/terminated/completed) to point at the next instruction, or if it is nullifying and the PSW address does not have to be incremented. So let's not modify the PSW address outside of the injection path and handle this internally. We just have to handle instruction length auto detection if no valid instruction length can be provided. This should fix various program interrupt injection paths, where the PSW was not properly forwarded. Signed-off-by: David Hildenbrand Message-Id: <20170609142156.18767-3-david@redhat.com> Signed-off-by: Richard Henderson --- target/s390x/cpu.h | 7 ++----- target/s390x/helper.c | 44 +++++++++++++++++++++++++++++++++++-------= -- target/s390x/misc_helper.c | 21 ++++++++------------- target/s390x/mmu_helper.c | 6 +++--- target/s390x/translate.c | 3 +-- 5 files changed, 49 insertions(+), 32 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index a4d31df..2954974 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -460,11 +460,6 @@ static inline bool get_per_in_range(CPUS390XState *env= , uint64_t addr) } =20 #ifndef CONFIG_USER_ONLY -/* In several cases of runtime exceptions, we havn't recorded the true - instruction length. Use these codes when raising exceptions in order - to re-compute the length by examining the insn in memory. */ -#define ILEN_LATER 0x20 -#define ILEN_LATER_INC 0x21 void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ile= n); #endif =20 @@ -1133,6 +1128,8 @@ uint32_t set_cc_nz_f128(float128 v); int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3); void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3); #endif +/* automatically detect the instruction length */ +#define ILEN_AUTO 0xff void program_interrupt(CPUS390XState *env, uint32_t code, int ilen); void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp, uintptr_t retaddr); diff --git a/target/s390x/helper.c b/target/s390x/helper.c index a8d20c5..aef09e1 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -204,7 +204,7 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_= vaddr, if (raddr > ram_size) { DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__, (uint64_t)raddr, (uint64_t)ram_size); - trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_LATER_INC); + trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO); return 1; } =20 @@ -331,16 +331,42 @@ static void do_program_interrupt(CPUS390XState *env) LowCore *lowcore; int ilen =3D env->int_pgm_ilen; =20 - switch (ilen) { - case ILEN_LATER: - ilen =3D get_ilen(cpu_ldub_code(env, env->psw.addr)); - break; - case ILEN_LATER_INC: + if (ilen =3D=3D ILEN_AUTO) { ilen =3D get_ilen(cpu_ldub_code(env, env->psw.addr)); + } + assert(ilen =3D=3D 2 || ilen =3D=3D 4 || ilen =3D=3D 6); + + switch (env->int_pgm_code) { + case PGM_PER: + if (env->per_perc_atmid & PER_CODE_EVENT_NULLIFICATION) { + break; + } + /* FALL THROUGH */ + case PGM_OPERATION: + case PGM_PRIVILEGED: + case PGM_EXECUTE: + case PGM_PROTECTION: + case PGM_ADDRESSING: + case PGM_SPECIFICATION: + case PGM_DATA: + case PGM_FIXPT_OVERFLOW: + case PGM_FIXPT_DIVIDE: + case PGM_DEC_OVERFLOW: + case PGM_DEC_DIVIDE: + case PGM_HFP_EXP_OVERFLOW: + case PGM_HFP_EXP_UNDERFLOW: + case PGM_HFP_SIGNIFICANCE: + case PGM_HFP_DIVIDE: + case PGM_TRANS_SPEC: + case PGM_SPECIAL_OP: + case PGM_OPERAND: + case PGM_HFP_SQRT: + case PGM_PC_TRANS_SPEC: + case PGM_ALET_SPEC: + case PGM_MONITOR: + /* advance the PSW if our exception is not nullifying */ env->psw.addr +=3D ilen; break; - default: - assert(ilen =3D=3D 2 || ilen =3D=3D 4 || ilen =3D=3D 6); } =20 qemu_log_mask(CPU_LOG_INT, "%s: code=3D0x%x ilen=3D%d\n", @@ -737,6 +763,6 @@ void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr = addr, if (retaddr) { cpu_restore_state(cs, retaddr); } - program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER); + program_interrupt(env, PGM_SPECIFICATION, ILEN_AUTO); } #endif /* CONFIG_USER_ONLY */ diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c index d6eda83..4daa016 100644 --- a/target/s390x/misc_helper.c +++ b/target/s390x/misc_helper.c @@ -54,19 +54,14 @@ void QEMU_NORETURN runtime_exception(CPUS390XState *env= , int excp, uintptr_t retaddr) { CPUState *cs =3D CPU(s390_env_get_cpu(env)); - int t; =20 cs->exception_index =3D EXCP_PGM; env->int_pgm_code =3D excp; + env->int_pgm_ilen =3D ILEN_AUTO; =20 /* Use the (ultimate) callers address to find the insn that trapped. = */ cpu_restore_state(cs, retaddr); =20 - /* Advance past the insn. */ - t =3D cpu_ldub_code(env, env->psw.addr); - env->int_pgm_ilen =3D t =3D get_ilen(t); - env->psw.addr +=3D t; - cpu_loop_exit(cs); } =20 @@ -199,12 +194,12 @@ void handle_diag_308(CPUS390XState *env, uint64_t r1,= uint64_t r3) IplParameterBlock *iplb; =20 if (env->psw.mask & PSW_MASK_PSTATE) { - program_interrupt(env, PGM_PRIVILEGED, ILEN_LATER_INC); + program_interrupt(env, PGM_PRIVILEGED, ILEN_AUTO); return; } =20 if ((subcode & ~0x0ffffULL) || (subcode > 6)) { - program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER_INC); + program_interrupt(env, PGM_SPECIFICATION, ILEN_AUTO); return; } =20 @@ -229,12 +224,12 @@ void handle_diag_308(CPUS390XState *env, uint64_t r1,= uint64_t r3) break; case 5: if ((r1 & 1) || (addr & 0x0fffULL)) { - program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER_INC); + program_interrupt(env, PGM_SPECIFICATION, ILEN_AUTO); return; } if (!address_space_access_valid(&address_space_memory, addr, sizeof(IplParameterBlock), false))= { - program_interrupt(env, PGM_ADDRESSING, ILEN_LATER_INC); + program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO); return; } iplb =3D g_malloc0(sizeof(IplParameterBlock)); @@ -258,12 +253,12 @@ out: return; case 6: if ((r1 & 1) || (addr & 0x0fffULL)) { - program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER_INC); + program_interrupt(env, PGM_SPECIFICATION, ILEN_AUTO); return; } if (!address_space_access_valid(&address_space_memory, addr, sizeof(IplParameterBlock), true)) { - program_interrupt(env, PGM_ADDRESSING, ILEN_LATER_INC); + program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO); return; } iplb =3D s390_ipl_get_iplb(); @@ -307,7 +302,7 @@ void HELPER(diag)(CPUS390XState *env, uint32_t r1, uint= 32_t r3, uint32_t num) } =20 if (r) { - program_interrupt(env, PGM_OPERATION, ILEN_LATER_INC); + program_interrupt(env, PGM_OPERATION, ILEN_AUTO); } } =20 diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index 501e390..a873dc4 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -79,13 +79,13 @@ static void trigger_prot_fault(CPUS390XState *env, targ= et_ulong vaddr, return; } =20 - trigger_access_exception(env, PGM_PROTECTION, ILEN_LATER_INC, tec); + trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, tec); } =20 static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, uint32_t type, uint64_t asc, int rw, bool e= xc) { - int ilen =3D ILEN_LATER; + int ilen =3D ILEN_AUTO; uint64_t tec; =20 tec =3D vaddr | (rw =3D=3D MMU_DATA_STORE ? FS_WRITE : FS_READ) | asc = >> 46; @@ -431,7 +431,7 @@ static int translate_pages(S390CPU *cpu, vaddr addr, in= t nr_pages, for (i =3D 0; i < nr_pages; i++) { /* Low-address protection? */ if (lowprot && (addr < 512 || (addr >=3D 4096 && addr < 4096 + 512= ))) { - trigger_access_exception(env, PGM_PROTECTION, ILEN_LATER_INC, = 0); + trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, 0); return -EACCES; } ret =3D mmu_translate(env, addr, is_write, asc, &pages[i], &pflags= , true); diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 95f91d4..d2917e4 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -355,8 +355,7 @@ static void gen_program_exception(DisasContext *s, int = code) tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen)); tcg_temp_free_i32(tmp); =20 - /* Advance past instruction. */ - s->pc =3D s->next_pc; + /* update the psw */ update_psw_addr(s); =20 /* Save off cc. */ --=20 2.9.4 From nobody Sat Feb 7 06:50:17 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1497385806344740.3965711926901; Tue, 13 Jun 2017 13:30:06 -0700 (PDT) Received: from localhost ([::1]:45080 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKsRw-0005hT-TY for importer@patchew.org; Tue, 13 Jun 2017 16:30:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40018) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKsP8-00037J-TK for qemu-devel@nongnu.org; Tue, 13 Jun 2017 16:27:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dKsP7-000442-Q8 for qemu-devel@nongnu.org; Tue, 13 Jun 2017 16:27:10 -0400 Received: from mail-qt0-x241.google.com ([2607:f8b0:400d:c0d::241]:36630) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dKsP7-00043p-Kp for qemu-devel@nongnu.org; Tue, 13 Jun 2017 16:27:09 -0400 Received: by mail-qt0-x241.google.com with SMTP id s33so37659243qtg.3 for ; Tue, 13 Jun 2017 13:27:09 -0700 (PDT) Received: from bigtime.twiddle.net.com (97-113-165-157.tukw.qwest.net. [97.113.165.157]) by smtp.gmail.com with ESMTPSA id j65sm9528787qkf.38.2017.06.13.13.27.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 13 Jun 2017 13:27:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=XfrvRCaDVt0vaUpu/TrPTSsdTK4AyptrJIe236pKe8U=; b=MPpwcYOiWEy45YQXK+/wO8XJ1zOEtRpkPo4AnSIKi06545fIytAKPhKKZ/2f3gQWbO oVTdmOm6JHfeAOZqz9C9ctMTKDRpZDgKGEjdx09vaxzpslUkEHuGYFUTRJERH9fRBQ8w DX8+ysIGWR6rjVI1/32KPt7Dec96+YEE2fiBMRHPYWaCjGyGIOppXpD2Z5k9evbLmrKR gWyCpnuj1pYHhFQnPmG8WXQYHe9ov/+LaIMycxdvpYuvcKB6hbIqsWHAaaT0x3nLVQtN vHbsvnOojmbHxWdgcRhQzUOK2Pf8tgOuOiIk/1rmqDffkt+WHyeTzvTCAQsp4CWVpii6 MQ9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=XfrvRCaDVt0vaUpu/TrPTSsdTK4AyptrJIe236pKe8U=; b=bbvHSciLsudkLMqNJwp8ua2Q7YwfrzeXDy7DK3ov7Nme6yGmoW5Bihxk6a8lFMFjH+ 4VC3XcifTnNEth9xEDk0sBGG3Sc1xTd317VHRuyh4O84HqBHEQlYmccAHt4PjKJPaK6Z tNLrto0AockCnNGdyY59mOX3ywW1ol2u5mZkQtKAdwgw/JHwB2kl1D6hOm5kfvjMdxXH GKxENhLEA2tgV97wqA4hSvCQgsEPboSMNDSKwkR/1FFpuNQCBiJrkrPRQ9Roh8fpbLLp a15vI23oIeKYneAxF1EAjWv7hbNLZDZndBO3e7VmkcoGcbc0lsCn9iaM6eeCHYxIQyxf lcdA== X-Gm-Message-State: AKS2vOyYLWqvJNZ84YQmtn5oNwbr++b52N97ePA+IvwiCvZ5PkQKak+l ctLN9o9BVgpKcTSSwmA= X-Received: by 10.200.40.251 with SMTP id j56mr2606722qtj.186.1497385628952; Tue, 13 Jun 2017 13:27:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 13 Jun 2017 13:26:59 -0700 Message-Id: <20170613202659.1920-4-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170613202659.1920-1-rth@twiddle.net> References: <20170613202659.1920-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::241 Subject: [Qemu-devel] [PULL 3/3] s390x/cpumodel: wire up cpu type + id for TCG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, David Hildenbrand Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: David Hildenbrand Let's properly expose the CPU type (machine-type number) via "STORE CPU ID" and "STORE SUBSYSTEM INFORMATION". As TCG emulates basic mode, the CPU identification number has the format "Annnnn", whereby A is the CPU address, and n are parts of the CPU serial number (0 for us for now). A specification exception will be injected if the address is not aligned to a double word. Low address protection will not be checked as we're missing some more general support for that. Signed-off-by: David Hildenbrand Message-Id: <20170609133426.11447-3-david@redhat.com> Signed-off-by: Richard Henderson --- target/s390x/cpu.h | 2 +- target/s390x/cpu_models.c | 8 ++++++-- target/s390x/insn-data.def | 2 +- target/s390x/misc_helper.c | 9 ++++++--- target/s390x/translate.c | 9 ++------- 5 files changed, 16 insertions(+), 14 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 2954974..a4028fb 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -149,7 +149,7 @@ typedef struct CPUS390XState { CPU_COMMON =20 uint32_t cpu_num; - uint32_t machine_type; + uint64_t cpuid; =20 uint64_t tod_offset; uint64_t tod_basetime; diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c index b34318f..478bcc6 100644 --- a/target/s390x/cpu_models.c +++ b/target/s390x/cpu_models.c @@ -737,8 +737,6 @@ static inline void apply_cpu_model(const S390CPUModel *= model, Error **errp) =20 if (kvm_enabled()) { kvm_s390_apply_cpu_model(model, errp); - } else if (model) { - /* FIXME TCG - use data for stdip/stfl */ } =20 if (!*errp) { @@ -786,6 +784,12 @@ void s390_realize_cpu_model(CPUState *cs, Error **errp) } =20 apply_cpu_model(cpu->model, errp); + + cpu->env.cpuid =3D s390_cpuid_from_cpu_model(cpu->model); + if (tcg_enabled()) { + /* basic mode, write the cpu address into the first 4 bit of the I= D */ + cpu->env.cpuid =3D deposit64(cpu->env.cpuid, 54, 4, cpu->env.cpu_n= um); + } } =20 static void get_feature(Object *obj, Visitor *v, const char *name, diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 73dd05d..d089707 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -960,7 +960,7 @@ /* STORE CPU ADDRESS */ C(0xb212, STAP, S, Z, la2, 0, new, m1_16, stap, 0) /* STORE CPU ID */ - C(0xb202, STIDP, S, Z, la2, 0, new, m1_64, stidp, 0) + C(0xb202, STIDP, S, Z, la2, 0, new, 0, stidp, 0) /* STORE CPU TIMER */ C(0xb209, STPT, S, Z, la2, 0, new, m1_64, stpt, 0) /* STORE FACILITY LIST */ diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c index 4daa016..b508101 100644 --- a/target/s390x/misc_helper.c +++ b/target/s390x/misc_helper.c @@ -378,6 +378,7 @@ uint64_t HELPER(stpt)(CPUS390XState *env) uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, uint64_t r0, uint64_t r1) { + S390CPU *cpu =3D s390_env_get_cpu(env); int cc =3D 0; int sel1, sel2; =20 @@ -397,12 +398,14 @@ uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, if ((sel1 =3D=3D 1) && (sel2 =3D=3D 1)) { /* Basic Machine Configuration */ struct sysib_111 sysib; + char type[5] =3D {}; =20 memset(&sysib, 0, sizeof(sysib)); ebcdic_put(sysib.manuf, "QEMU ", 16); - /* same as machine type number in STORE CPU ID */ - ebcdic_put(sysib.type, "QEMU", 4); - /* same as model number in STORE CPU ID */ + /* same as machine type number in STORE CPU ID, but in EBCDIC = */ + snprintf(type, ARRAY_SIZE(type), "%X", cpu->model->def->type); + ebcdic_put(sysib.type, type, 4); + /* model number (not stored in STORE CPU ID for z/Architecure)= */ ebcdic_put(sysib.model, "QEMU ", 16); ebcdic_put(sysib.sequence, "QEMU ", 16); ebcdic_put(sysib.plant, "QEMU", 4); diff --git a/target/s390x/translate.c b/target/s390x/translate.c index d2917e4..8c055b7 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -3876,14 +3876,9 @@ static ExitStatus op_stctl(DisasContext *s, DisasOps= *o) =20 static ExitStatus op_stidp(DisasContext *s, DisasOps *o) { - TCGv_i64 t1 =3D tcg_temp_new_i64(); - check_privileged(s); - tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num)); - tcg_gen_ld32u_i64(t1, cpu_env, offsetof(CPUS390XState, machine_type)); - tcg_gen_deposit_i64(o->out, o->out, t1, 32, 32); - tcg_temp_free_i64(t1); - + tcg_gen_ld_i64(o->out, cpu_env, offsetof(CPUS390XState, cpuid)); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEQ | MO_AL= IGN); return NO_EXIT; } =20 --=20 2.9.4