From nobody Wed Nov 5 16:36:19 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496948195548522.9301217395437; Thu, 8 Jun 2017 11:56:35 -0700 (PDT) Received: from localhost ([::1]:51065 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dJ2bg-0002Db-JN for importer@patchew.org; Thu, 08 Jun 2017 14:56:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47333) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dJ2Vb-0005oP-1r for qemu-devel@nongnu.org; Thu, 08 Jun 2017 14:50:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dJ2VZ-0001Po-EK for qemu-devel@nongnu.org; Thu, 08 Jun 2017 14:50:15 -0400 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:36355) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dJ2VZ-0001Oi-4m for qemu-devel@nongnu.org; Thu, 08 Jun 2017 14:50:13 -0400 Received: by mail-wm0-x242.google.com with SMTP id d17so3821402wme.3 for ; Thu, 08 Jun 2017 11:50:12 -0700 (PDT) Received: from a0999b0126e1.ant.amazon.com ([2.53.26.197]) by smtp.gmail.com with ESMTPSA id z32sm2914198edb.8.2017.06.08.11.50.09 (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 08 Jun 2017 11:50:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jMOHk2DRYnj8Z+s5JYcaKP17o2ew3lKfp+HTLhjxKZc=; b=NTqXtnmg6gpujeO9/2/jN0S4bowpYSWClaLP4pW7Wmd/TmnbI8B/BtDFOXOAGR4UG9 6O/ogj7D7tHXcNZKokV1dvZGXFICuaQ1CeG4BQ9O0cTzsdIziI+ndDay/dAgeLLnifSg YO3MgKFupf3dsHCMcBjWFi+BRRd6iY5eT7jY3r00ZZiWVOLx2bYUiumoA8/kcS24vBRB hXV0Us7BXNZO/vjQwmblaj7C1cgP7f9gMGDjUeyPoKM7E1o/1LI70BuaPwsleSCQ8dLW dN4zcoT/dCYNg8M1KSS3UvoSX5s10cjiwtqxJcIwqxL7wuS1ZKwaROHo3s4XB2HBhApu rksQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jMOHk2DRYnj8Z+s5JYcaKP17o2ew3lKfp+HTLhjxKZc=; b=bG4p98Y+3mO0PJQoBNEg0ZWxVvPfJLszV6axenOHf84ynpRRts+A/CplUkGTXTy89H uReZ8NM0gWOiZ9V861YMzCvX7Pt4Gd+E6aJaZnAo3Om7PCKJYbZt7Y9b/OFE8C61e4h5 2J1gD6s8NE93oqjoeoJ5fOtUcYYgq9pwWbQgNg1/VBNRte3qmOi1kQ8p0lswFg5Jzwm2 9YUovu/sP1yAkL9HDdE5prnBuFmhOpIqhKAfcsN3yVLvOxhsCk8alVOvgTUWXUlIGPuH BxICSFbfHVf5yDjhlo5ajcodIkOwDY4jLGSLTLB9C1QM6o4yrgBsaUOeuGfsugJ9pARI YXoA== X-Gm-Message-State: AODbwcDcddJHIEpOaw5xvs5n57btCWBzI/1SkbrMmKnbejZnyJllhcY8 zkwAENQGJ44ep5IaBco= X-Received: by 10.80.193.130 with SMTP id m2mr29962181edf.85.1496947811860; Thu, 08 Jun 2017 11:50:11 -0700 (PDT) From: Michael Rolnik To: qemu-devel@nongnu.org Date: Thu, 8 Jun 2017 21:49:41 +0300 Message-Id: <20170608184944.19406-7-mrolnik@gmail.com> X-Mailer: git-send-email 2.11.0 (Apple Git-81) In-Reply-To: <20170608184944.19406-1-mrolnik@gmail.com> References: <20170608184944.19406-1-mrolnik@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH RFC v19 06/13] target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Michael Rolnik , anichang@protonmail.ch Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Michael Rolnik Message-Id: <1471522070-77598-7-git-send-email-mrolnik@gmail.com> Signed-off-by: Richard Henderson --- target/avr/cpu.h | 10 +++ target/avr/helper.c | 216 +++++++++++++++++++++++++++++++++++++++++++++= +++- target/avr/helper.h | 7 ++ target/avr/translate.c | 8 ++ 4 files changed, 239 insertions(+), 2 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 54dc58c0df..92143244f7 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -139,6 +139,7 @@ struct CPUAVRState { uint32_t sp; /* 16 bits */ =20 uint64_t intsrc; /* interrupt sources */ + bool fullacc;/* CPU/MEM if true MEM only otherwise */ =20 uint32_t features; =20 @@ -181,6 +182,10 @@ int avr_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr= ess, int rw, int avr_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf, int len, bool is_write); =20 +enum { + TB_FLAGS_FULL_ACCESS =3D 1, +}; + static inline void cpu_get_tb_cpu_state(CPUAVRState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { @@ -188,6 +193,11 @@ static inline void cpu_get_tb_cpu_state(CPUAVRState *e= nv, target_ulong *pc, =20 *pc =3D env->pc_w * 2; *cs_base =3D 0; + + if (env->fullacc) { + flags |=3D TB_FLAGS_FULL_ACCESS; + } + *pflags =3D flags; } =20 diff --git a/target/avr/helper.c b/target/avr/helper.c index 61255fdff3..bc53053a57 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -28,6 +28,7 @@ #include "exec/cpu_ldst.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" +#include "exec/ioport.h" =20 bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { @@ -79,11 +80,11 @@ void avr_cpu_do_interrupt(CPUState *cs) =20 if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) { cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); - cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8); + cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8); cpu_stb_data(env, env->sp--, (ret & 0xff0000) >> 16); } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) { cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); - cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8); + cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8); } else { cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); } @@ -126,7 +127,19 @@ void tlb_fill(CPUState *cs, target_ulong vaddr, MMUAcc= essType access_type, if (mmu_idx =3D=3D MMU_CODE_IDX) { paddr =3D PHYS_BASE_CODE + vaddr - VIRT_BASE_CODE; prot =3D PAGE_READ | PAGE_EXEC; + } else if (vaddr - VIRT_BASE_REGS < AVR_REGS) { + /* + * this is a write into CPU registers, exit and rebuilt this TB + * to use full write + */ + AVRCPU *cpu =3D AVR_CPU(cs); + CPUAVRState *env =3D &cpu->env; + env->fullacc =3D 1; + cpu_loop_exit_restore(cs, retaddr); } else { + /* + * this is a write into memory. nothing special + */ paddr =3D PHYS_BASE_DATA + vaddr - VIRT_BASE_DATA; prot =3D PAGE_READ | PAGE_WRITE; } @@ -134,6 +147,30 @@ void tlb_fill(CPUState *cs, target_ulong vaddr, MMUAcc= essType access_type, tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, prot, mmu_idx, page_s= ize); } =20 +void helper_sleep(CPUAVRState *env) +{ + CPUState *cs =3D CPU(avr_env_get_cpu(env)); + + cs->exception_index =3D EXCP_HLT; + cpu_loop_exit(cs); +} + +void helper_unsupported(CPUAVRState *env) +{ + CPUState *cs =3D CPU(avr_env_get_cpu(env)); + + /* + * I count not find what happens on the real platform, so + * it's EXCP_DEBUG for meanwhile + */ + cs->exception_index =3D EXCP_DEBUG; + if (qemu_loglevel_mask(LOG_UNIMP)) { + qemu_log("UNSUPPORTED\n"); + cpu_dump_state(cs, qemu_logfile, fprintf, 0); + } + cpu_loop_exit(cs); +} + void helper_debug(CPUAVRState *env) { CPUState *cs =3D CPU(avr_env_get_cpu(env)); @@ -141,3 +178,178 @@ void helper_debug(CPUAVRState *env) cs->exception_index =3D EXCP_DEBUG; cpu_loop_exit(cs); } + +void helper_wdr(CPUAVRState *env) +{ + CPUState *cs =3D CPU(avr_env_get_cpu(env)); + + /* WD is not implemented yet, placeholder */ + cs->exception_index =3D EXCP_DEBUG; + cpu_loop_exit(cs); +} + +/* + * This function implements IN instruction + * + * It does the following + * a. if an IO register belongs to CPU, its value is read and returned + * b. otherwise io address is translated to mem address and physical memo= ry + * is read. + * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation + * + */ +target_ulong helper_inb(CPUAVRState *env, uint32_t port) +{ + target_ulong data =3D 0; + + switch (port) { + case 0x38: /* RAMPD */ + data =3D 0xff & (env->rampD >> 16); + break; + case 0x39: /* RAMPX */ + data =3D 0xff & (env->rampX >> 16); + break; + case 0x3a: /* RAMPY */ + data =3D 0xff & (env->rampY >> 16); + break; + case 0x3b: /* RAMPZ */ + data =3D 0xff & (env->rampZ >> 16); + break; + case 0x3c: /* EIND */ + data =3D 0xff & (env->eind >> 16); + break; + case 0x3d: /* SPL */ + data =3D env->sp & 0x00ff; + break; + case 0x3e: /* SPH */ + data =3D env->sp >> 8; + break; + case 0x3f: /* SREG */ + data =3D cpu_get_sreg(env); + break; + default: + /* + * CPU does not know how to read this register, pass it to the + * device/board + */ + cpu_physical_memory_read(PHYS_BASE_REGS + port + AVR_CPU_IO_REGS_B= ASE, + &data, 1); + } + + return data; +} + +/* + * This function implements OUT instruction + * + * It does the following + * a. if an IO register belongs to CPU, its value is written into the re= gister + * b. otherwise io address is translated to mem address and physical mem= ory + * is written. + * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementati= on + * + */ +void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data) +{ + data &=3D 0x000000ff; + + switch (port) { + case 0x04: + { + CPUState *cpu =3D CPU(avr_env_get_cpu(env)); + qemu_irq irq =3D qdev_get_gpio_in(DEVICE(cpu), 3); + qemu_set_irq(irq, 1); + } + break; + case 0x38: /* RAMPD */ + if (avr_feature(env, AVR_FEATURE_RAMPD)) { + env->rampD =3D (data & 0xff) << 16; + } + break; + case 0x39: /* RAMPX */ + if (avr_feature(env, AVR_FEATURE_RAMPX)) { + env->rampX =3D (data & 0xff) << 16; + } + break; + case 0x3a: /* RAMPY */ + if (avr_feature(env, AVR_FEATURE_RAMPY)) { + env->rampY =3D (data & 0xff) << 16; + } + break; + case 0x3b: /* RAMPZ */ + if (avr_feature(env, AVR_FEATURE_RAMPZ)) { + env->rampZ =3D (data & 0xff) << 16; + } + break; + case 0x3c: /* EIDN */ + env->eind =3D (data & 0xff) << 16; + break; + case 0x3d: /* SPL */ + env->sp =3D (env->sp & 0xff00) | (data); + break; + case 0x3e: /* SPH */ + if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) { + env->sp =3D (env->sp & 0x00ff) | (data << 8); + } + break; + case 0x3f: /* SREG */ + cpu_set_sreg(env, data); + break; + default: + /* + * CPU does not know how to write this register, pass it to the + * device/board + */ + cpu_physical_memory_write(PHYS_BASE_REGS + port + AVR_CPU_IO_REGS_= BASE, + &data, 1); + } +} + +/* + * this function implements LD instruction when there is a posibility to = read + * from a CPU register + */ +target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr) +{ + uint8_t data; + + env->fullacc =3D false; + switch (addr) { + case AVR_CPU_REGS_BASE ... AVR_CPU_REGS_LAST: + /* CPU registers */ + data =3D env->r[addr - AVR_CPU_REGS_BASE]; + break; + case AVR_CPU_IO_REGS_BASE ... AVR_CPU_IO_REGS_LAST: + /* CPU IO registers */ + data =3D helper_inb(env, addr); + break; + default: + /* memory */ + cpu_physical_memory_read(PHYS_BASE_DATA + addr - VIRT_BASE_DATA, + &data, 1); + } + return data; +} + +/* + * this function implements LD instruction when there is a posibility to = write + * into a CPU register + */ +void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr) +{ + env->fullacc =3D false; + switch (addr) { + case AVR_CPU_REGS_BASE ... AVR_CPU_REGS_LAST: + /* CPU registers */ + env->r[addr - AVR_CPU_REGS_BASE] =3D data; + break; + case AVR_CPU_IO_REGS_BASE ... AVR_CPU_IO_REGS_LAST: + /* CPU IO registers */ + helper_outb(env, data, addr); + break; + default: + /* memory */ + cpu_physical_memory_write(PHYS_BASE_DATA + addr - VIRT_BASE_DATA, + &data, 1); + } +} diff --git a/target/avr/helper.h b/target/avr/helper.h index b5ef3bfb93..603631520a 100644 --- a/target/avr/helper.h +++ b/target/avr/helper.h @@ -18,4 +18,11 @@ * */ =20 +DEF_HELPER_1(wdr, void, env) DEF_HELPER_1(debug, void, env) +DEF_HELPER_1(sleep, void, env) +DEF_HELPER_1(unsupported, void, env) +DEF_HELPER_3(outb, void, env, i32, i32) +DEF_HELPER_2(inb, tl, env, i32) +DEF_HELPER_3(fullwr, void, env, i32, i32) +DEF_HELPER_2(fullrd, tl, env, i32) diff --git a/target/avr/translate.c b/target/avr/translate.c index 7926b7162f..daf4a6afc7 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -128,6 +128,14 @@ void gen_intermediate_code(CPUAVRState *env, struct Tr= anslationBlock *tb) if (max_insns > TCG_MAX_INSNS) { max_insns =3D TCG_MAX_INSNS; } + if (tb->flags & TB_FLAGS_FULL_ACCESS) { + /* + this flag is set by ST/LD instruction + we will regenerate it ONLY with mem/cpu memory access + instead of mem access + */ + max_insns =3D 1; + } =20 gen_tb_start(tb); =20 --=20 2.11.0 (Apple Git-81)