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[71.217.91.69]) by smtp.gmail.com with ESMTPSA id m47sm29286qtc.36.2017.06.06.17.32.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Jun 2017 17:32:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=7a3iQgtqjF4MGFYtEPLUDPYXk8cmX+UfI0+5XXAwDLI=; b=s0zjT0rR544wbiTH+SeSFkT84ShWTTZ9n9F8TdFN10oTTgGZTR+mAuUFZ0LBCSNDn4 ZYqKJ0BYv5cx1jnD4zO3d1yPnM+eyz/MVhSpomGY5pTvaIF5wmV4s4hnPL2vlOSjJxcs SPZ2vsQfZvmIc4vT49h2zxEG9KCHTbvC79vdrQJbNt+riKHsO/Pi755T14jb0SE8yDs/ kwwzcPeMMphgbx7JTcqlnjRYrBl4WkNE/Mwb0pskwEsTKIOnpVGcdIHC/T+r5FRXbMoY SA72BChkanCQ1hSe32mSLa4tAkF6xFmdcuP/Z7eECgAl6ANipm1pTO/TkhiKwYYqazZj ogRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=7a3iQgtqjF4MGFYtEPLUDPYXk8cmX+UfI0+5XXAwDLI=; b=k9mNR9BsINtUyHR5VMElvtOOSziVHcTGEfca/1Ienn4sh6vQX4n2zInbMSuTzMxqGx GuWGsV6333WnRB3r/Xaa7kAZRvokADDNWDyqEdxBEbcAofM/NHvp7AHZyMjyEEY+QODX RxXL35NjGmnITGXUcnt5lMPy3UtQ0lVHN6K3IBV6qLgMMjBzzbO4c8g9tb3gA5QZblCv wC5zl/gPkCBd0PCdaRsOIiVBGU2QsafZMNZXtgRPy08nR7ZgJ1fJpXC2t0eNbC30JJ3A h2A2KCgy1nQVE0TpmEgfG+EWCSaxLPDxY6h5eDyJxG/F9+aNTUsCzv/rgL2vMY+AKSLo i/Ew== X-Gm-Message-State: AODbwcAmrk1F9UNf3pYDs+LXUNZ9jTGKgNnjpdJq4wszCnH+Cm+6+32X brxCkS4QJU8u2oMFonw= X-Received: by 10.55.88.199 with SMTP id m190mr35061646qkb.56.1496795569989; Tue, 06 Jun 2017 17:32:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 6 Jun 2017 17:31:14 -0700 Message-Id: <20170607003119.14778-66-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170607003119.14778-1-rth@twiddle.net> References: <20170607003119.14778-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-devel] [PULL v2 65/70] target/s390x: implement TRANSLATE ONE/TWO TO ONE/TWO X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aurelien Jarno Signed-off-by: Aurelien Jarno Message-Id: <20170531220129.27724-29-aurelien@aurel32.net> Signed-off-by: Richard Henderson --- target/s390x/helper.h | 1 + target/s390x/insn-data.def | 9 +++++++++ target/s390x/mem_helper.c | 45 ++++++++++++++++++++++++++++++++++++++++++= +++ target/s390x/translate.c | 30 ++++++++++++++++++++++++++++++ 4 files changed, 85 insertions(+) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 5871568..11a545e 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -95,6 +95,7 @@ DEF_HELPER_FLAGS_3(tp, TCG_CALL_NO_WG, i32, env, i64, i32) DEF_HELPER_FLAGS_4(tr, TCG_CALL_NO_WG, void, env, i32, i64, i64) DEF_HELPER_4(tre, i64, env, i64, i64, i64) DEF_HELPER_4(trt, i32, env, i32, i64, i64) +DEF_HELPER_5(trXX, i32, env, i32, i32, i32, i32) DEF_HELPER_4(cksm, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_5(calc_cc, TCG_CALL_NO_RWG_SE, i32, env, i32, i64, i64, i= 64) DEF_HELPER_FLAGS_2(sfpc, TCG_CALL_NO_RWG, void, env, i64) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 7db5133..9976d29 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -870,6 +870,15 @@ /* TRANSLATE EXTENDED */ C(0xb2a5, TRE, RRE, Z, 0, r2, r1_P, 0, tre, 0) =20 +/* TRANSLATE ONE TO ONE */ + C(0xb993, TROO, RRF_c, E2, 0, 0, 0, 0, trXX, 0) +/* TRANSLATE ONE TO TWO */ + C(0xb992, TROT, RRF_c, E2, 0, 0, 0, 0, trXX, 0) +/* TRANSLATE TWO TO ONE */ + C(0xb991, TRTO, RRF_c, E2, 0, 0, 0, 0, trXX, 0) +/* TRANSLATE TWO TO TWO */ + C(0xb990, TRTT, RRF_c, E2, 0, 0, 0, 0, trXX, 0) + /* UNPACK */ /* Really format SS_b, but we pack both lengths into one argument for the helper call, so we might as well leave one 8-bit field. */ diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index fa2bfbb..be89cc4 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1196,6 +1196,51 @@ uint32_t HELPER(trt)(CPUS390XState *env, uint32_t le= n, uint64_t array, return do_helper_trt(env, len, array, trans, GETPC()); } =20 +/* Translate one/two to one/two */ +uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t r1, uint32_t r2, + uint32_t tst, uint32_t sizes) +{ + uintptr_t ra =3D GETPC(); + int dsize =3D (sizes & 1) ? 1 : 2; + int ssize =3D (sizes & 2) ? 1 : 2; + uint64_t tbl =3D get_address(env, 1) & ~7; + uint64_t dst =3D get_address(env, r1); + uint64_t len =3D get_length(env, r1 + 1); + uint64_t src =3D get_address(env, r2); + uint32_t cc =3D 3; + int i; + + check_alignment(env, len, ssize, ra); + + /* Lest we fail to service interrupts in a timely manner, */ + /* limit the amount of work we're willing to do. */ + for (i =3D 0; i < 0x2000; i++) { + uint16_t sval =3D cpu_ldusize_data_ra(env, src, ssize, ra); + uint64_t tble =3D tbl + (sval * dsize); + uint16_t dval =3D cpu_ldusize_data_ra(env, tble, dsize, ra); + if (dval =3D=3D tst) { + cc =3D 1; + break; + } + cpu_stsize_data_ra(env, dst, dval, dsize, ra); + + len -=3D ssize; + src +=3D ssize; + dst +=3D dsize; + + if (len =3D=3D 0) { + cc =3D 0; + break; + } + } + + set_address(env, r1, dst); + set_length(env, r1 + 1, len); + set_address(env, r2, src); + + return cc; +} + void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, uint32_t r1, uint32_t r3) { diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 2253ce6..9f3443e 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -4340,6 +4340,36 @@ static ExitStatus op_trt(DisasContext *s, DisasOps *= o) return NO_EXIT; } =20 +static ExitStatus op_trXX(DisasContext *s, DisasOps *o) +{ + TCGv_i32 r1 =3D tcg_const_i32(get_field(s->fields, r1)); + TCGv_i32 r2 =3D tcg_const_i32(get_field(s->fields, r2)); + TCGv_i32 sizes =3D tcg_const_i32(s->insn->opc & 3); + TCGv_i32 tst =3D tcg_temp_new_i32(); + int m3 =3D get_field(s->fields, m3); + + /* XXX: the C bit in M3 should be considered as 0 when the + ETF2-enhancement facility is not installed. */ + if (m3 & 1) { + tcg_gen_movi_i32(tst, -1); + } else { + tcg_gen_extrl_i64_i32(tst, regs[0]); + if (s->insn->opc & 3) { + tcg_gen_ext8u_i32(tst, tst); + } else { + tcg_gen_ext16u_i32(tst, tst); + } + } + gen_helper_trXX(cc_op, cpu_env, r1, r2, tst, sizes); + + tcg_temp_free_i32(r1); + tcg_temp_free_i32(r2); + tcg_temp_free_i32(sizes); + tcg_temp_free_i32(tst); + set_cc_static(s); + return NO_EXIT; +} + static ExitStatus op_ts(DisasContext *s, DisasOps *o) { TCGv_i32 t1 =3D tcg_const_i32(0xff); --=20 2.9.4