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[71.217.91.69]) by smtp.gmail.com with ESMTPSA id m47sm29286qtc.36.2017.06.06.17.32.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Jun 2017 17:32:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=/kr8ps84mVKBjpfIXGC8Z9DgOi3pc9TVx3w/2qYjHEI=; b=pPNUR+o2nwBzioP9sujGqjc1fNpNacIQZ16CjMzKzJEJJhFKlZZ/1Ded7KPI9m7l/M IzT2XKFXxleGqZN/waDv0M1bN6F5RgIBwGivy2h5atc0vgGYULuB0MLRXzwA2TkivHuu G4XNj38B/7VqIVXfsLPcdiWkdpWpBiZ8z5ajSixewhpaqc6wL+x7NBD0q8OSD7wfsWNN 0QOPYey+KG4sOy0XjjMKPEbg0BPh6POyIl+OsW9Ag9QKBNvvwzDilFVNg8qr6udaQyRa hxJ9wdUcpq+tOkuNRXrxojgW07+VCyirFsPTqgM68slSigtad6HXCuaVE3ppJUCMfvJN 1efQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=/kr8ps84mVKBjpfIXGC8Z9DgOi3pc9TVx3w/2qYjHEI=; b=ltPH+OdqIx5mFAVfL8Mi7mCfqND/vew3Va6+F8iyfH2e1xhkKKthIgB3IktW0dSfx1 SgEHjf47Zzwm8/753/2Edbvg6hnyOsD8iXxSInsqeOqbkySMazJwmguUKDkVsniML7la fZ1NvPxDrn28VFeIWk4s5l5720UBPump/fu51Ood15SGFDtVRM4Rb9n9U5QT2WIYQ4Zf x6/tNHHxCePo5Y2OznAveDJt+ECKgRGvQS/ez+4RLUoYdp7jcbyHlLJPFU2WrH3a9k32 LjDk/0PA4oJAtBrkeyLjuHVRdr1Lm4jJIkuNAcIJs7JcKwj2m2ZxvPHjV98gfUmxX3iD FYew== X-Gm-Message-State: AODbwcC2DL2WHPONvw58JiwEcb2zhZ/GN2EOoonrzGObSLO2ES8W9fxC WZ6Vs1vGXCpKxRfaRzY= X-Received: by 10.200.45.83 with SMTP id o19mr27553262qta.43.1496795533997; Tue, 06 Jun 2017 17:32:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 6 Jun 2017 17:30:47 -0700 Message-Id: <20170607003119.14778-39-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170607003119.14778-1-rth@twiddle.net> References: <20170607003119.14778-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::244 Subject: [Qemu-devel] [PULL v2 38/70] target/s390x: Re-implement a few EXECUTE target insns directly X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" While the previous patch is required for proper conformance, the vast majority of target insns are MVC and XC for implementing memmove and memset respectively. The next most common are CLC, TR, and SVC. Implementing these (and a few others for which we already have an implementation) directly is faster than going through full translation to a TB. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- target/s390x/mem_helper.c | 66 ++++++++++++++++++++++++++++++++++++-------= ---- 1 file changed, 51 insertions(+), 15 deletions(-) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 3a77edc..e35571e 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -200,31 +200,30 @@ uint32_t HELPER(oc)(CPUS390XState *env, uint32_t l, u= int64_t dest, } =20 /* memmove */ -static void do_helper_mvc(CPUS390XState *env, uint32_t l, uint64_t dest, - uint64_t src, uintptr_t ra) +static uint32_t do_helper_mvc(CPUS390XState *env, uint32_t l, uint64_t des= t, + uint64_t src, uintptr_t ra) { uint32_t i; =20 HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n", __func__, l, dest, src); =20 + /* mvc and memmove do not behave the same when areas overlap! */ /* mvc with source pointing to the byte after the destination is the same as memset with the first source byte */ if (dest =3D=3D src + 1) { fast_memset(env, dest, cpu_ldub_data_ra(env, src, ra), l + 1, ra); - return; - } - - /* mvc and memmove do not behave the same when areas overlap! */ - if (dest < src || src + l < dest) { + } else if (dest < src || src + l < dest) { fast_memmove(env, dest, src, l + 1, ra); - return; + } else { + /* slow version with byte accesses which always work */ + for (i =3D 0; i <=3D l; i++) { + uint8_t x =3D cpu_ldub_data_ra(env, src + i, ra); + cpu_stb_data_ra(env, dest + i, x, ra); + } } =20 - /* slow version with byte accesses which always work */ - for (i =3D 0; i <=3D l; i++) { - cpu_stb_data_ra(env, dest + i, cpu_ldub_data_ra(env, src + i, ra),= ra); - } + return env->cc_op; } =20 void HELPER(mvc)(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t s= rc) @@ -692,8 +691,8 @@ void HELPER(unpk)(CPUS390XState *env, uint32_t len, uin= t64_t dest, } } =20 -static void do_helper_tr(CPUS390XState *env, uint32_t len, uint64_t array, - uint64_t trans, uintptr_t ra) +static uint32_t do_helper_tr(CPUS390XState *env, uint32_t len, uint64_t ar= ray, + uint64_t trans, uintptr_t ra) { uint32_t i; =20 @@ -702,12 +701,14 @@ static void do_helper_tr(CPUS390XState *env, uint32_t= len, uint64_t array, uint8_t new_byte =3D cpu_ldub_data_ra(env, trans + byte, ra); cpu_stb_data_ra(env, array + i, new_byte, ra); } + + return env->cc_op; } =20 void HELPER(tr)(CPUS390XState *env, uint32_t len, uint64_t array, uint64_t trans) { - return do_helper_tr(env, len, array, trans, GETPC()); + do_helper_tr(env, len, array, trans, GETPC()); } =20 uint64_t HELPER(tre)(CPUS390XState *env, uint64_t array, @@ -1221,6 +1222,41 @@ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, u= int64_t r1, uint64_t addr) g_assert_not_reached(); } =20 + /* The very most common cases can be sped up by avoiding a new TB. */ + if ((opc & 0xf0) =3D=3D 0xd0) { + typedef uint32_t (*dx_helper)(CPUS390XState *, uint32_t, uint64_t, + uint64_t, uintptr_t); + static const dx_helper dx[16] =3D { + [0x2] =3D do_helper_mvc, + [0x4] =3D do_helper_nc, + [0x5] =3D do_helper_clc, + [0x6] =3D do_helper_oc, + [0x7] =3D do_helper_xc, + [0xc] =3D do_helper_tr, + [0xd] =3D do_helper_trt, + }; + dx_helper helper =3D dx[opc & 0xf]; + + if (helper) { + uint32_t l =3D extract64(insn, 48, 8); + uint32_t b1 =3D extract64(insn, 44, 4); + uint32_t d1 =3D extract64(insn, 32, 12); + uint32_t b2 =3D extract64(insn, 28, 4); + uint32_t d2 =3D extract64(insn, 16, 12); + uint64_t a1 =3D get_address(env, 0, b1, d1); + uint64_t a2 =3D get_address(env, 0, b2, d2); + + env->cc_op =3D helper(env, l, a1, a2, 0); + env->psw.addr +=3D ilen; + return; + } + } else if (opc =3D=3D 0x0a) { + env->int_svc_code =3D extract64(insn, 48, 8); + env->int_svc_ilen =3D ilen; + helper_exception(env, EXCP_SVC); + g_assert_not_reached(); + } + /* Record the insn we want to execute as well as the ilen to use during the execution of the target insn. This will also ensure that ex_value is non-zero, which flags that we are in a state --=20 2.9.4