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[71.217.91.69]) by smtp.gmail.com with ESMTPSA id m47sm29286qtc.36.2017.06.06.17.32.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Jun 2017 17:32:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=pKdVMyq6NUl9Uax3AnPkTszRhUZ/SIxkkQqCZ8YdAmU=; b=AOJOln/Tekfoq/itrz0uOP14hVQ/66m9MmFij1BOO6N5/rLkuHIIbK3L1l8qevJhfH j56mkLA+YlFa7ceehGyTi5bPzWZ4nHkyBDHR2DPufaU99BXklPCYZRxr7+aIOLOXRJDi daaH8ssfbmJIZ9BrPhRxfYb0U8mpMtQirIE7UNObjOK9Gw98jM+Rg2BTCiKD/czDtTrS NJ9duL/1dc+XW9onjYVQY92QB0vgpdMSscgS28f6LdfmsZ7H6VjsIsGU59+Onx4YDq6K 6D137OW8qvrv3+ClSczTpIDOLr0xQg7wnm/JpmqYkv4N+8UHvyeumwW1u/LhP30P091k iZVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=pKdVMyq6NUl9Uax3AnPkTszRhUZ/SIxkkQqCZ8YdAmU=; b=CYMm+qBS25jHhm/WxXipWgAVeYWUCyXu/kKXgBQYOhiLqQjMYiyt3mbKWVwrB2HX5a 1MjN3Qcw2W9I9iiVwZSmINdWIl0ysMDm7Mc4L7Vu2CPY1Lx8G3unzSIjH1eO3cybmT2j Z4YMsEum4Q6V1Z01h/KiXq9gWHQx3iwyFVw7wirop97P6+IKYlJ43UBikbimF/UlxznT SdWCFGOozLAxuhjO3xNf8dGTxdPKPULz5ESo5+ii/fuYcMmTburgJpFsDei7TUzgXDia z4FwEsOedo0ztnD5rR4LlOqu1LVx24vgddHO0AMFwBPpW39TQzXsIQUIiXPjrjs5jBgK n+7A== X-Gm-Message-State: AKS2vOxxWBlT38zNkeF1JTishAJfkcvWXhxCBMjQF4NjSOijTh7oM1Xy YtEG/ofs1r1aderHYpY= X-Received: by 10.55.124.194 with SMTP id x185mr22152791qkc.215.1496795524846; Tue, 06 Jun 2017 17:32:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 6 Jun 2017 17:30:40 -0700 Message-Id: <20170607003119.14778-32-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170607003119.14778-1-rth@twiddle.net> References: <20170607003119.14778-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PULL v2 31/70] target/s390x: Fix some helper_ex problems X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" (1) The OR of the low bits or R1 into INSN were not being done consistently; it was forgotten along all but the SVC path. (2) The setting of ILEN was wrong on SVC path for EXRL. (3) The data load for ICM read too much. Fix these by consolidating data load at the beginning, using get_ilen to control the number of bytes loaded, and ORing in the byte from R1. Use extract64 from the full aligned insn to extract arguments. Pass in ILEN rather than RET as the more natural way to give the required data along the SVC path. Modify ENV->CC_OP directly rather than include it in the functional interface. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- target/s390x/helper.h | 2 +- target/s390x/mem_helper.c | 135 +++++++++++++++++++++++++-----------------= ---- target/s390x/translate.c | 8 +-- 3 files changed, 78 insertions(+), 67 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index ea35834..3819409 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -14,7 +14,7 @@ DEF_HELPER_4(srst, i64, env, i64, i64, i64) DEF_HELPER_4(clst, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(mvpg, TCG_CALL_NO_WG, i32, env, i64, i64, i64) DEF_HELPER_4(mvst, i64, env, i64, i64, i64) -DEF_HELPER_5(ex, i32, env, i32, i64, i64, i64) +DEF_HELPER_4(ex, void, env, i32, i64, i64) DEF_HELPER_FLAGS_4(stam, TCG_CALL_NO_WG, void, env, i32, i64, i32) DEF_HELPER_FLAGS_4(lam, TCG_CALL_NO_WG, void, env, i32, i64, i32) DEF_HELPER_4(mvcle, i32, env, i32, i64, i32) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index a73d486..fa03129 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1245,76 +1245,87 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t a= ddr) in other words: tricky... currently implemented by interpreting the cases it is most commonly use= d. */ -uint32_t HELPER(ex)(CPUS390XState *env, uint32_t cc, uint64_t v1, - uint64_t addr, uint64_t ret) +void HELPER(ex)(CPUS390XState *env, uint32_t ilen, uint64_t r1, uint64_t a= ddr) { S390CPU *cpu =3D s390_env_get_cpu(env); - uint16_t insn =3D cpu_lduw_code(env, addr); - - HELPER_LOG("%s: v1 0x%lx addr 0x%lx insn 0x%x\n", __func__, v1, addr, - insn); - if ((insn & 0xf0ff) =3D=3D 0xd000) { - uint32_t l, insn2, b1, b2, d1, d2; - - l =3D v1 & 0xff; - insn2 =3D cpu_ldl_code(env, addr + 2); - b1 =3D (insn2 >> 28) & 0xf; - b2 =3D (insn2 >> 12) & 0xf; - d1 =3D (insn2 >> 16) & 0xfff; - d2 =3D insn2 & 0xfff; - switch (insn & 0xf00) { - case 0x200: + uint64_t insn =3D cpu_lduw_code(env, addr); + uint8_t opc =3D insn >> 8; + + /* Or in the contents of R1[56:63]. */ + insn |=3D r1 & 0xff; + + /* Load the rest of the instruction. */ + insn <<=3D 48; + switch (get_ilen(opc)) { + case 2: + break; + case 4: + insn |=3D (uint64_t)cpu_lduw_code(env, addr + 2) << 32; + break; + case 6: + insn |=3D (uint64_t)(uint32_t)cpu_ldl_code(env, addr + 2) << 16; + break; + default: + g_assert_not_reached(); + } + + HELPER_LOG("%s: addr 0x%lx insn 0x%" PRIx64 "\n", __func__, addr, insn= ); + + if ((opc & 0xf0) =3D=3D 0xd0) { + uint32_t l, b1, b2, d1, d2; + + l =3D extract64(insn, 48, 8); + b1 =3D extract64(insn, 44, 4); + b2 =3D extract64(insn, 28, 4); + d1 =3D extract64(insn, 32, 12); + d2 =3D extract64(insn, 16, 12); + switch (opc & 0xf) { + case 0x2: do_helper_mvc(env, l, get_address(env, 0, b1, d1), get_address(env, 0, b2, d2), 0); - break; - case 0x400: - cc =3D do_helper_nc(env, l, get_address(env, 0, b1, d1), - get_address(env, 0, b2, d2), 0); - break; - case 0x500: - cc =3D do_helper_clc(env, l, get_address(env, 0, b1, d1), - get_address(env, 0, b2, d2), 0); - break; - case 0x600: - cc =3D do_helper_oc(env, l, get_address(env, 0, b1, d1), - get_address(env, 0, b2, d2), 0); - break; - case 0x700: - cc =3D do_helper_xc(env, l, get_address(env, 0, b1, d1), - get_address(env, 0, b2, d2), 0); - break; - case 0xc00: + return; + case 0x4: + env->cc_op =3D do_helper_nc(env, l, get_address(env, 0, b1, d1= ), + get_address(env, 0, b2, d2), 0); + return; + case 0x5: + env->cc_op =3D do_helper_clc(env, l, get_address(env, 0, b1, d= 1), + get_address(env, 0, b2, d2), 0); + return; + case 0x6: + env->cc_op =3D do_helper_oc(env, l, get_address(env, 0, b1, d1= ), + get_address(env, 0, b2, d2), 0); + return; + case 0x7: + env->cc_op =3D do_helper_xc(env, l, get_address(env, 0, b1, d1= ), + get_address(env, 0, b2, d2), 0); + return; + case 0xc: do_helper_tr(env, l, get_address(env, 0, b1, d1), get_address(env, 0, b2, d2), 0); - return cc; - case 0xd00: - cc =3D do_helper_trt(env, l, get_address(env, 0, b1, d1), - get_address(env, 0, b2, d2), 0); - break; - default: - goto abort; + return; + case 0xd: + env->cc_op =3D do_helper_trt(env, l, get_address(env, 0, b1, d= 1), + get_address(env, 0, b2, d2), 0); + return; } - } else if ((insn & 0xff00) =3D=3D 0x0a00) { + } else if (opc =3D=3D 0x0a) { /* supervisor call */ - HELPER_LOG("%s: svc %ld via execute\n", __func__, (insn | v1) & 0x= ff); - env->psw.addr =3D ret - 4; - env->int_svc_code =3D (insn | v1) & 0xff; - env->int_svc_ilen =3D 4; + env->int_svc_code =3D extract64(insn, 48, 8); + env->int_svc_ilen =3D ilen; helper_exception(env, EXCP_SVC); - } else if ((insn & 0xff00) =3D=3D 0xbf00) { - uint32_t insn2, r1, r3, b2, d2; - - insn2 =3D cpu_ldl_code(env, addr + 2); - r1 =3D (insn2 >> 20) & 0xf; - r3 =3D (insn2 >> 16) & 0xf; - b2 =3D (insn2 >> 12) & 0xf; - d2 =3D insn2 & 0xfff; - cc =3D helper_icm(env, r1, get_address(env, 0, b2, d2), r3); - } else { - abort: - cpu_abort(CPU(cpu), - "EXECUTE on instruction prefix 0x%x not implemented\n", - insn); + return; + } else if (opc =3D=3D 0xbf) { + uint32_t r1, r3, b2, d2; + + r1 =3D extract64(insn, 52, 4); + r3 =3D extract64(insn, 48, 4); + b2 =3D extract64(insn, 44, 4); + d2 =3D extract64(insn, 32, 12); + env->cc_op =3D helper_icm(env, r1, get_address(env, 0, b2, d2), r3= ); + return; } - return cc; + + cpu_abort(CPU(cpu), "EXECUTE on instruction prefix 0x%x not implemente= d\n", + opc); } diff --git a/target/s390x/translate.c b/target/s390x/translate.c index e99fbd9..c1162a1 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -2164,14 +2164,14 @@ static ExitStatus op_ex(DisasContext *s, DisasOps *= o) MVC inside of memcpy, which needs a helper call anyway. So perhaps this doesn't bear thinking about any further. */ =20 - TCGv_i64 tmp; + TCGv_i32 ilen; =20 update_psw_addr(s); gen_op_calc_cc(s); =20 - tmp =3D tcg_const_i64(s->next_pc); - gen_helper_ex(cc_op, cpu_env, cc_op, o->in1, o->in2, tmp); - tcg_temp_free_i64(tmp); + ilen =3D tcg_const_i32(s->next_pc - s->pc); + gen_helper_ex(cpu_env, ilen, o->in1, o->in2); + tcg_temp_free_i32(ilen); =20 return NO_EXIT; } --=20 2.9.4