From nobody Tue Feb 10 04:15:37 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496717770036285.5725252434578; Mon, 5 Jun 2017 19:56:10 -0700 (PDT) Received: from localhost ([::1]:35967 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dI4fA-0007WW-M5 for importer@patchew.org; Mon, 05 Jun 2017 22:56:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54277) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dI4ax-0003Ut-IC for qemu-devel@nongnu.org; Mon, 05 Jun 2017 22:51:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dI4aw-0002yS-Bq for qemu-devel@nongnu.org; Mon, 05 Jun 2017 22:51:47 -0400 Received: from ozlabs.org ([103.22.144.67]:52443) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dI4av-0002xZ-Vt; Mon, 05 Jun 2017 22:51:46 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 3whbmq2skYz9s9Y; Tue, 6 Jun 2017 12:51:39 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1496717499; bh=/zYz1kE6Gk+a1r9aExc6VpDY1W8j84lErEi/qxLWkRY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BEOELm1uy2eYylctyh+OM3bU3x0fTOawCGlP+kbBLhq+N7E4J1yILeWoLHmo2dfkz mVVZP4c1TW7lYktarwvDKx/Df5KLBIWDXQFYvMblZrNqEBzF3d+WCEmXkSUnMj3pi+ RzFJfvX1BgmlEYJkl9uo8hMF/VBcsYem7LToBRjo= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 6 Jun 2017 12:51:25 +1000 Message-Id: <20170606025135.2685-8-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170606025135.2685-1-david@gibson.dropbear.id.au> References: <20170606025135.2685-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 07/17] target-ppc: Fix openpic timer read register offset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, mdroth@linux.vnet.ibm.com, agraf@suse.de, qemu-ppc@nongnu.org, Aaron Larson , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aaron Larson openpic_tmr_read() is incorrectly computing register offset of the TCCR, TBCR, TVPR, and TDR registers when accessing the open pic timer registers. Specifically the offset of timer registers for openpic_tmr_read() is not accounting for the timer frequency reporting register (TFFR) which is the first register in the "tmr" memory region. openpic_tmr_write() *is* correctly computing the offset by adding 0x10f0 to the address prior to computing the register index. This patch instead subtracts 0x10 in both the read and write routines and eliminates some other gratuitous differences between the functions. Signed-off-by: Aaron Larson Signed-off-by: David Gibson --- hw/intc/openpic.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c index 4349e45..f966d06 100644 --- a/hw/intc/openpic.c +++ b/hw/intc/openpic.c @@ -796,27 +796,24 @@ static uint64_t openpic_gbl_read(void *opaque, hwaddr= addr, unsigned len) } =20 static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val, - unsigned len) + unsigned len) { OpenPICState *opp =3D opaque; int idx; =20 - addr +=3D 0x10f0; - DPRINTF("%s: addr %#" HWADDR_PRIx " <=3D %08" PRIx64 "\n", - __func__, addr, val); + __func__, (addr + 0x10f0), val); if (addr & 0xF) { return; } =20 - if (addr =3D=3D 0x10f0) { + if (addr =3D=3D 0) { /* TFRR */ opp->tfrr =3D val; return; } - + addr -=3D 0x10; /* correct for TFRR */ idx =3D (addr >> 6) & 0x3; - addr =3D addr & 0x30; =20 switch (addr & 0x30) { case 0x00: /* TCCR */ @@ -844,16 +841,17 @@ static uint64_t openpic_tmr_read(void *opaque, hwaddr= addr, unsigned len) uint32_t retval =3D -1; int idx; =20 - DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); + DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr + 0x10f0); if (addr & 0xF) { goto out; } - idx =3D (addr >> 6) & 0x3; - if (addr =3D=3D 0x0) { + if (addr =3D=3D 0) { /* TFRR */ retval =3D opp->tfrr; goto out; } + addr -=3D 0x10; /* correct for TFRR */ + idx =3D (addr >> 6) & 0x3; switch (addr & 0x30) { case 0x00: /* TCCR */ retval =3D opp->timers[idx].tccr; @@ -861,10 +859,10 @@ static uint64_t openpic_tmr_read(void *opaque, hwaddr= addr, unsigned len) case 0x10: /* TBCR */ retval =3D opp->timers[idx].tbcr; break; - case 0x20: /* TIPV */ + case 0x20: /* TVPR */ retval =3D read_IRQreg_ivpr(opp, opp->irq_tim0 + idx); break; - case 0x30: /* TIDE (TIDR) */ + case 0x30: /* TDR */ retval =3D read_IRQreg_idr(opp, opp->irq_tim0 + idx); break; } --=20 2.9.4