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[98.155.27.246]) by smtp.gmail.com with ESMTPSA id j191sm52854419pgc.53.2017.06.04.10.35.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 04 Jun 2017 10:35:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZbdnupYWtSaqaWBVaKxg4uD14LABlehwujsNfxC/Ls8=; b=mZo0R/gXtwXYybj+GhanwfwPOX1JFn+qebKTonGQrDi7Urmw4evpK0kizDFfoSkik4 1KtTVZPmRbpvlcizXHEgZMLSRhtRCmTCx/20uQ14HWUPkodXeO20AkDNfCRQpj9RtXga qpfKNo3Boxk/40VhWm5EwFguNwT4c0KcocUKaR+HqZH8KVC/cKJ7mOQM7J1SvYxI1WA4 EWZYFnUZGAiwys1ypigyJCk3Ojecs6sFsVspOiV+7OVAxe7jgY/nrwInmGyYreW7QZIT 96sxKgt9TG6OXfK4ixWsx71j3j3RTqgFA4gRQ7IKneI5npDZZMyDMsKSelzA69H5S4Mw oNkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=ZbdnupYWtSaqaWBVaKxg4uD14LABlehwujsNfxC/Ls8=; b=RNHIGXS4rA92DvChYYfgqiIdIf8o0s4qd5pA5vFsu9L4o3x2zmlzrS9UVvnyGi3O5y 7C6cr3wBaqXPN7l02iWjYZDD4i6Q2R1Ywmhz2wik1+X9xWLD5cbCnQhBwUHe/bKuL0TS gOoRveIaC9627m8c0l+1xFgOaTDP9pk3hw4qWcxcyUTLgi5+rQV6Bsl5yYWJ8t7l6hvc kXkDDURmbct/Uow3CTTLZcdUbIC947ciOAbv61MKtMWrOKyt9OPBLjCXRZ21eifJK0OF b64pe8sAMNrcYFM3Hcg8EUBvvvSLBC/GxnWm9v9fjAEt+PyggHBVD4snwF0At5BKbYEz 2xDw== X-Gm-Message-State: AODbwcDddUSG1yPHwrfkPp19OAxN57Jl/9eWND7OC4wX1+t3BabvdqQm iRwjOZ4khMtMTmmOd+0= X-Received: by 10.101.89.66 with SMTP id g2mr2587689pgu.146.1496597716587; Sun, 04 Jun 2017 10:35:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 4 Jun 2017 10:34:03 -0700 Message-Id: <20170604173509.29684-4-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170604173509.29684-1-rth@twiddle.net> References: <20170604173509.29684-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PULL 03/69] target/s390x: Move helper_ex to end of file X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This will avoid needing forward declarations in following patches. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- target/s390x/mem_helper.c | 161 +++++++++++++++++++++++-------------------= ---- 1 file changed, 81 insertions(+), 80 deletions(-) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index e3325a4..90b62fa 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -436,86 +436,6 @@ static uint32_t helper_icm(CPUS390XState *env, uint32_= t r1, uint64_t address, return cc; } =20 -/* execute instruction - this instruction executes an insn modified with the contents of r1 - it does not change the executed instruction in memory - it does not change the program counter - in other words: tricky... - currently implemented by interpreting the cases it is most commonly use= d in -*/ -uint32_t HELPER(ex)(CPUS390XState *env, uint32_t cc, uint64_t v1, - uint64_t addr, uint64_t ret) -{ - S390CPU *cpu =3D s390_env_get_cpu(env); - uint16_t insn =3D cpu_lduw_code(env, addr); - - HELPER_LOG("%s: v1 0x%lx addr 0x%lx insn 0x%x\n", __func__, v1, addr, - insn); - if ((insn & 0xf0ff) =3D=3D 0xd000) { - uint32_t l, insn2, b1, b2, d1, d2; - - l =3D v1 & 0xff; - insn2 =3D cpu_ldl_code(env, addr + 2); - b1 =3D (insn2 >> 28) & 0xf; - b2 =3D (insn2 >> 12) & 0xf; - d1 =3D (insn2 >> 16) & 0xfff; - d2 =3D insn2 & 0xfff; - switch (insn & 0xf00) { - case 0x200: - helper_mvc(env, l, get_address(env, 0, b1, d1), - get_address(env, 0, b2, d2)); - break; - case 0x400: - cc =3D helper_nc(env, l, get_address(env, 0, b1, d1), - get_address(env, 0, b2, d2)); - break; - case 0x500: - cc =3D helper_clc(env, l, get_address(env, 0, b1, d1), - get_address(env, 0, b2, d2)); - break; - case 0x600: - cc =3D helper_oc(env, l, get_address(env, 0, b1, d1), - get_address(env, 0, b2, d2)); - break; - case 0x700: - cc =3D helper_xc(env, l, get_address(env, 0, b1, d1), - get_address(env, 0, b2, d2)); - break; - case 0xc00: - helper_tr(env, l, get_address(env, 0, b1, d1), - get_address(env, 0, b2, d2)); - break; - case 0xd00: - cc =3D helper_trt(env, l, get_address(env, 0, b1, d1), - get_address(env, 0, b2, d2)); - break; - default: - goto abort; - } - } else if ((insn & 0xff00) =3D=3D 0x0a00) { - /* supervisor call */ - HELPER_LOG("%s: svc %ld via execute\n", __func__, (insn | v1) & 0x= ff); - env->psw.addr =3D ret - 4; - env->int_svc_code =3D (insn | v1) & 0xff; - env->int_svc_ilen =3D 4; - helper_exception(env, EXCP_SVC); - } else if ((insn & 0xff00) =3D=3D 0xbf00) { - uint32_t insn2, r1, r3, b2, d2; - - insn2 =3D cpu_ldl_code(env, addr + 2); - r1 =3D (insn2 >> 20) & 0xf; - r3 =3D (insn2 >> 16) & 0xf; - b2 =3D (insn2 >> 12) & 0xf; - d2 =3D insn2 & 0xfff; - cc =3D helper_icm(env, r1, get_address(env, 0, b2, d2), r3); - } else { - abort: - cpu_abort(CPU(cpu), "EXECUTE on instruction prefix 0x%x not implem= ented\n", - insn); - } - return cc; -} - /* load access registers r1 to r3 from memory at a2 */ void HELPER(lam)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) { @@ -1262,3 +1182,84 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t ad= dr) return ret; } #endif + +/* execute instruction + this instruction executes an insn modified with the contents of r1 + it does not change the executed instruction in memory + it does not change the program counter + in other words: tricky... + currently implemented by interpreting the cases it is most commonly use= d. +*/ +uint32_t HELPER(ex)(CPUS390XState *env, uint32_t cc, uint64_t v1, + uint64_t addr, uint64_t ret) +{ + S390CPU *cpu =3D s390_env_get_cpu(env); + uint16_t insn =3D cpu_lduw_code(env, addr); + + HELPER_LOG("%s: v1 0x%lx addr 0x%lx insn 0x%x\n", __func__, v1, addr, + insn); + if ((insn & 0xf0ff) =3D=3D 0xd000) { + uint32_t l, insn2, b1, b2, d1, d2; + + l =3D v1 & 0xff; + insn2 =3D cpu_ldl_code(env, addr + 2); + b1 =3D (insn2 >> 28) & 0xf; + b2 =3D (insn2 >> 12) & 0xf; + d1 =3D (insn2 >> 16) & 0xfff; + d2 =3D insn2 & 0xfff; + switch (insn & 0xf00) { + case 0x200: + helper_mvc(env, l, get_address(env, 0, b1, d1), + get_address(env, 0, b2, d2)); + break; + case 0x400: + cc =3D helper_nc(env, l, get_address(env, 0, b1, d1), + get_address(env, 0, b2, d2)); + break; + case 0x500: + cc =3D helper_clc(env, l, get_address(env, 0, b1, d1), + get_address(env, 0, b2, d2)); + break; + case 0x600: + cc =3D helper_oc(env, l, get_address(env, 0, b1, d1), + get_address(env, 0, b2, d2)); + break; + case 0x700: + cc =3D helper_xc(env, l, get_address(env, 0, b1, d1), + get_address(env, 0, b2, d2)); + break; + case 0xc00: + helper_tr(env, l, get_address(env, 0, b1, d1), + get_address(env, 0, b2, d2)); + break; + case 0xd00: + cc =3D helper_trt(env, l, get_address(env, 0, b1, d1), + get_address(env, 0, b2, d2)); + break; + default: + goto abort; + } + } else if ((insn & 0xff00) =3D=3D 0x0a00) { + /* supervisor call */ + HELPER_LOG("%s: svc %ld via execute\n", __func__, (insn | v1) & 0x= ff); + env->psw.addr =3D ret - 4; + env->int_svc_code =3D (insn | v1) & 0xff; + env->int_svc_ilen =3D 4; + helper_exception(env, EXCP_SVC); + } else if ((insn & 0xff00) =3D=3D 0xbf00) { + uint32_t insn2, r1, r3, b2, d2; + + insn2 =3D cpu_ldl_code(env, addr + 2); + r1 =3D (insn2 >> 20) & 0xf; + r3 =3D (insn2 >> 16) & 0xf; + b2 =3D (insn2 >> 12) & 0xf; + d2 =3D insn2 & 0xfff; + cc =3D helper_icm(env, r1, get_address(env, 0, b2, d2), r3); + } else { + abort: + cpu_abort(CPU(cpu), + "EXECUTE on instruction prefix 0x%x not implemented\n", + insn); + } + return cc; +} --=20 2.9.4