From nobody Wed Nov 5 16:41:02 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496404142875854.7280881605768; Fri, 2 Jun 2017 04:49:02 -0700 (PDT) Received: from localhost ([::1]:49181 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGl4f-0006WN-BN for importer@patchew.org; Fri, 02 Jun 2017 07:49:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39407) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGkpQ-0000Lk-9M for qemu-devel@nongnu.org; Fri, 02 Jun 2017 07:33:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGkpM-00047u-Bc for qemu-devel@nongnu.org; Fri, 02 Jun 2017 07:33:16 -0400 Received: from linux03.ddci.com ([184.183.10.182]:58788 helo=linux03a.ddci.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dGkpM-000446-1g; Fri, 02 Jun 2017 07:33:12 -0400 Received: from linux03a.ddci.com (localhost.localdomain [127.0.0.1]) by linux03a.ddci.com (8.13.8/8.13.8) with ESMTP id v52BX24C027536; Fri, 2 Jun 2017 04:33:02 -0700 Received: (from alarson@localhost) by linux03a.ddci.com (8.13.8/8.13.8/Submit) id v52BWx1t027533; Fri, 2 Jun 2017 04:32:59 -0700 Date: Fri, 2 Jun 2017 04:32:59 -0700 From: Aaron Larson Message-Id: <201706021132.v52BWx1t027533@linux03a.ddci.com> To: agraf@suse.de, alarson@ddci.com, david@gibson.dropbear.id.au, qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 184.183.10.182 Subject: [Qemu-devel] [PATCH] target-ppc: Fix openpic timer read register offset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" openpic_tmr_read() is incorrectly computing register offset of the TCCR, TBCR, TVPR, and TDR registers when accessing the open pic timer registers. Specifically the offset of timer registers for openpic_tmr_read() is not accounting for the timer frequency reporting register (TFFR) which is the first register in the "tmr" memory region. openpic_tmr_write() *is* correctly computing the offset by adding 0x10f0 to the address prior to computing the register index. This patch instead subtracts 0x10 in both the read and write routines and eliminates some other gratuitous differences between the functions. Signed-off-by: Aaron Larson --- hw/intc/openpic.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c index 4349e45..f966d06 100644 --- a/hw/intc/openpic.c +++ b/hw/intc/openpic.c @@ -796,27 +796,24 @@ static uint64_t openpic_gbl_read(void *opaque, hwaddr= addr, unsigned len) } =20 static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val, - unsigned len) + unsigned len) { OpenPICState *opp =3D opaque; int idx; =20 - addr +=3D 0x10f0; - DPRINTF("%s: addr %#" HWADDR_PRIx " <=3D %08" PRIx64 "\n", - __func__, addr, val); + __func__, (addr + 0x10f0), val); if (addr & 0xF) { return; } =20 - if (addr =3D=3D 0x10f0) { + if (addr =3D=3D 0) { /* TFRR */ opp->tfrr =3D val; return; } - + addr -=3D 0x10; /* correct for TFRR */ idx =3D (addr >> 6) & 0x3; - addr =3D addr & 0x30; =20 switch (addr & 0x30) { case 0x00: /* TCCR */ @@ -844,16 +841,17 @@ static uint64_t openpic_tmr_read(void *opaque, hwaddr= addr, unsigned len) uint32_t retval =3D -1; int idx; =20 - DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); + DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr + 0x10f0); if (addr & 0xF) { goto out; } - idx =3D (addr >> 6) & 0x3; - if (addr =3D=3D 0x0) { + if (addr =3D=3D 0) { /* TFRR */ retval =3D opp->tfrr; goto out; } + addr -=3D 0x10; /* correct for TFRR */ + idx =3D (addr >> 6) & 0x3; switch (addr & 0x30) { case 0x00: /* TCCR */ retval =3D opp->timers[idx].tccr; @@ -861,10 +859,10 @@ static uint64_t openpic_tmr_read(void *opaque, hwaddr= addr, unsigned len) case 0x10: /* TBCR */ retval =3D opp->timers[idx].tbcr; break; - case 0x20: /* TIPV */ + case 0x20: /* TVPR */ retval =3D read_IRQreg_ivpr(opp, opp->irq_tim0 + idx); break; - case 0x30: /* TIDE (TIDR) */ + case 0x30: /* TDR */ retval =3D read_IRQreg_idr(opp, opp->irq_tim0 + idx); break; } --=20 2.7.4