From nobody Tue Apr 30 01:16:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1495663808573896.8573824512089; Wed, 24 May 2017 15:10:08 -0700 (PDT) Received: from localhost ([::1]:57027 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dDeTn-0000Jq-25 for importer@patchew.org; Wed, 24 May 2017 18:10:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57332) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dDeSJ-0007ZE-QN for qemu-devel@nongnu.org; Wed, 24 May 2017 18:08:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dDeSI-00055c-RF for qemu-devel@nongnu.org; Wed, 24 May 2017 18:08:35 -0400 Received: from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:35939) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dDeSI-00054W-MF for qemu-devel@nongnu.org; Wed, 24 May 2017 18:08:34 -0400 Received: by mail-qk0-x243.google.com with SMTP id y128so28223777qka.3 for ; Wed, 24 May 2017 15:08:34 -0700 (PDT) Received: from bigtime.twiddle.net.com ([2602:47:d954:1500:5e51:4fff:fe40:9c64]) by smtp.gmail.com with ESMTPSA id y188sm3347693qkb.49.2017.05.24.15.08.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 24 May 2017 15:08:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=mhguX5dNK5WwQNfGqKcuW76eUpWBSSLaiy0fhhg4zRg=; b=FCzKJ0HN+SkAW/8UdVipD4QOfM/3ymvND9BElrFlqHAhOG6k0CtG3MiQxJD4XGlG0i CGJU+rjCRcap9GrnSYC3iEFOPGNd0FqWv1XCZqaIGfWct1KaDn5CMs4uyQT+0F+o83C9 3z/V1rRKSOxCFdAAKpPgeAkaYoCHIzCrg9iTSOvVy7XPZ8Uqee7w2GJ3Cu4YZ/SheGZk u3NaJs+K4NtH1pbbsNgS40SCV/u6cS1PgJazqIG6ouVxFLXI4NYyAsISTsxJcoZrX/IY Gcnky1LYMj2I2QMeOTAIgEhhtLg4455vpXiANoIti+EKRWDeUh8r5dIinMkLh5D+n5gV yMxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=mhguX5dNK5WwQNfGqKcuW76eUpWBSSLaiy0fhhg4zRg=; b=HTGCMhayIm8//I5Lw2JERJa/o/klyueXkzB0LDbw0gVYWmavfUN8dQqLoWVZaLXKD2 v9iYk6Y8DmH/BWxZUQ1V55HzFKn28rRKRS8fjiRxVSLGYB02XMz9wtE99a7d9NBfY8eD ikVAjkRVt/UY/1kGNj72s+qgjWoxpzVybjiJo3+6IAjV8cLnSyt7U+90BaPy5yXmfCeR h9EWNeaeT5uwhDOlrAO7PSir24RhiMtUvy6ZrjygIsX7Cj3b5ZiZHeu96lASP++njxhO tDkaewXrKBroKgjO1w77UQlaBVLJQweAfJmp9U98w81sZXFuM8gi+EDuzal7drr9Amx9 oOiA== X-Gm-Message-State: AODbwcBFm4exjSv268OrJa3U6BHmx2M7d1TuTmwnp/vYvjbLG92F13sc g5PT0PsNCW9Ahg== X-Received: by 10.55.88.194 with SMTP id m185mr14550698qkb.230.1495663714004; Wed, 24 May 2017 15:08:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 May 2017 15:08:24 -0700 Message-Id: <20170524220827.21154-2-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170524220827.21154-1-rth@twiddle.net> References: <20170524220827.21154-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH 1/4] target/s390x: Save current ilen during translation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Use this saved value instead of recomputing from next_pc difference. Signed-off-by: Richard Henderson Reviewed-by: Aurelien Jarno Reviewed-by: David Hildenbrand --- target/s390x/translate.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 4bd16d9..5b8333f 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -58,6 +58,7 @@ struct DisasContext { const DisasInsn *insn; DisasFields *fields; uint64_t pc, next_pc; + uint32_t ilen; enum cc_op cc_op; bool singlestep_enabled; }; @@ -349,7 +350,7 @@ static void gen_program_exception(DisasContext *s, int = code) tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code)); tcg_temp_free_i32(tmp); =20 - tmp =3D tcg_const_i32(s->next_pc - s->pc); + tmp =3D tcg_const_i32(s->ilen); tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen)); tcg_temp_free_i32(tmp); =20 @@ -2207,7 +2208,7 @@ static ExitStatus op_ex(DisasContext *s, DisasOps *o) v1 =3D regs[r1]; } =20 - ilen =3D tcg_const_i32(s->next_pc - s->pc); + ilen =3D tcg_const_i32(s->ilen); gen_helper_ex(cpu_env, ilen, v1, o->in2); tcg_temp_free_i32(ilen); =20 @@ -4052,7 +4053,7 @@ static ExitStatus op_svc(DisasContext *s, DisasOps *o) tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code)); tcg_temp_free_i32(t); =20 - t =3D tcg_const_i32(s->next_pc - s->pc); + t =3D tcg_const_i32(s->ilen); tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen)); tcg_temp_free_i32(t); =20 @@ -5191,6 +5192,7 @@ static const DisasInsn *extract_insn(CPUS390XState *e= nv, DisasContext *s, op =3D (insn >> 8) & 0xff; ilen =3D get_ilen(op); s->next_pc =3D s->pc + ilen; + s->ilen =3D ilen; =20 switch (ilen) { case 2: --=20 2.9.4 From nobody Tue Apr 30 01:16:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH 2/4] target/s390x: End the TB after EXECUTE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This split will be required for implementing EXECUTE properly. Do this now as a separate step to aid comparison of before and after TB listings. Signed-off-by: Richard Henderson Reviewed-by: Aurelien Jarno --- target/s390x/mem_helper.c | 54 ++++++++++++++++++++++++++++---------------= ---- target/s390x/translate.c | 6 +++++- 2 files changed, 37 insertions(+), 23 deletions(-) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 4b96c27..d57d5b1 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1234,6 +1234,7 @@ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, ui= nt64_t r1, uint64_t addr) S390CPU *cpu =3D s390_env_get_cpu(env); uint64_t insn =3D cpu_lduw_code(env, addr); uint8_t opc =3D insn >> 8; + uint32_t cc; =20 /* Or in the contents of R1[56:63]. */ insn |=3D r1 & 0xff; @@ -1263,42 +1264,46 @@ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, = uint64_t r1, uint64_t addr) b2 =3D extract64(insn, 28, 4); d1 =3D extract64(insn, 32, 12); d2 =3D extract64(insn, 16, 12); + + cc =3D env->cc_op; switch (opc & 0xf) { case 0x2: do_helper_mvc(env, l, get_address(env, 0, b1, d1), get_address(env, 0, b2, d2), 0); - return; + break; case 0x4: - env->cc_op =3D do_helper_nc(env, l, get_address(env, 0, b1, d1= ), - get_address(env, 0, b2, d2), 0); - return; + cc =3D do_helper_nc(env, l, get_address(env, 0, b1, d1), + get_address(env, 0, b2, d2), 0); + break; case 0x5: - env->cc_op =3D do_helper_clc(env, l, get_address(env, 0, b1, d= 1), - get_address(env, 0, b2, d2), 0); - return; + cc =3D do_helper_clc(env, l, get_address(env, 0, b1, d1), + get_address(env, 0, b2, d2), 0); + break; case 0x6: - env->cc_op =3D do_helper_oc(env, l, get_address(env, 0, b1, d1= ), - get_address(env, 0, b2, d2), 0); - return; + cc =3D do_helper_oc(env, l, get_address(env, 0, b1, d1), + get_address(env, 0, b2, d2), 0); + break; case 0x7: - env->cc_op =3D do_helper_xc(env, l, get_address(env, 0, b1, d1= ), - get_address(env, 0, b2, d2), 0); - return; + cc =3D do_helper_xc(env, l, get_address(env, 0, b1, d1), + get_address(env, 0, b2, d2), 0); + break; case 0xc: do_helper_tr(env, l, get_address(env, 0, b1, d1), get_address(env, 0, b2, d2), 0); - return; + break; case 0xd: - env->cc_op =3D do_helper_trt(env, l, get_address(env, 0, b1, d= 1), - get_address(env, 0, b2, d2), 0); - return; + cc =3D do_helper_trt(env, l, get_address(env, 0, b1, d1), + get_address(env, 0, b2, d2), 0); + break; + default: + goto abort; } } else if (opc =3D=3D 0x0a) { /* supervisor call */ env->int_svc_code =3D extract64(insn, 48, 8); env->int_svc_ilen =3D ilen; helper_exception(env, EXCP_SVC); - return; + g_assert_not_reached(); } else if (opc =3D=3D 0xbf) { uint32_t r1, r3, b2, d2; =20 @@ -1306,10 +1311,15 @@ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, = uint64_t r1, uint64_t addr) r3 =3D extract64(insn, 48, 4); b2 =3D extract64(insn, 44, 4); d2 =3D extract64(insn, 32, 12); - env->cc_op =3D helper_icm(env, r1, get_address(env, 0, b2, d2), r3= ); - return; + cc =3D helper_icm(env, r1, get_address(env, 0, b2, d2), r3); + } else { + abort: + cpu_abort(CPU(cpu), + "EXECUTE on instruction prefix 0x%x not implemented\n", + opc); + g_assert_not_reached(); } =20 - cpu_abort(CPU(cpu), "EXECUTE on instruction prefix 0x%x not implemente= d\n", - opc); + env->cc_op =3D cc; + env->psw.addr +=3D ilen; } diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 5b8333f..70212c8 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -1163,6 +1163,8 @@ typedef enum { the PC (for whatever reason), so there's no need to do it again on exiting the TB. */ EXIT_PC_UPDATED, + /* We have updated the PC and CC values. */ + EXIT_PC_CC_UPDATED, /* We are exiting the TB, but have neither emitted a goto_tb, nor updated the PC for the next instruction to be executed. */ EXIT_PC_STALE, @@ -2216,7 +2218,7 @@ static ExitStatus op_ex(DisasContext *s, DisasOps *o) tcg_temp_free_i64(v1); } =20 - return NO_EXIT; + return EXIT_PC_CC_UPDATED; } =20 static ExitStatus op_fieb(DisasContext *s, DisasOps *o) @@ -5489,6 +5491,8 @@ void gen_intermediate_code(CPUS390XState *env, struct= TranslationBlock *tb) /* Next TB starts off with CC_OP_DYNAMIC, so make sure the cc op type is in env */ update_cc_op(&dc); + /* FALLTHRU */ + case EXIT_PC_CC_UPDATED: /* Exit the TB, either by raising a debug exception or by return. = */ if (do_debug) { gen_exception(EXCP_DEBUG); --=20 2.9.4 From nobody Tue Apr 30 01:16:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1495663969924317.8239674836366; Wed, 24 May 2017 15:12:49 -0700 (PDT) Received: from localhost ([::1]:57039 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dDeWO-0002Bo-Jj for importer@patchew.org; Wed, 24 May 2017 18:12:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57360) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dDeSO-0007fr-FV for qemu-devel@nongnu.org; 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Wed, 24 May 2017 15:08:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 May 2017 15:08:26 -0700 Message-Id: <20170524220827.21154-4-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170524220827.21154-1-rth@twiddle.net> References: <20170524220827.21154-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-devel] [PATCH 3/4] target/s390x: Implement EXECUTE via new TranslationBlock X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Previously, helper_ex would construct the insn and then implement the insn via direct calls other helpers. This was sufficient to boot Linux but that is all. It is easy enough to go the whole nine yards by stashing state for EXECUTE within the cpu, and then rely on a new TB to be created that properly and completely interprets the insn. Signed-off-by: Richard Henderson Reviewed-by: Aurelien Jarno --- target/s390x/cpu.h | 4 +- target/s390x/helper.c | 5 ++ target/s390x/machine.c | 19 ++++++++ target/s390x/mem_helper.c | 118 +++++-------------------------------------= ---- target/s390x/translate.c | 80 ++++++++++++++++++------------- 5 files changed, 85 insertions(+), 141 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 4f38ba0..79235cf 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -103,6 +103,8 @@ typedef struct CPUS390XState { uint64_t cc_dst; uint64_t cc_vr; =20 + uint64_t ex_value; + uint64_t __excp_addr; uint64_t psa; =20 @@ -391,7 +393,7 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState* = env, target_ulong *pc, target_ulong *cs_base, uint32_t *f= lags) { *pc =3D env->psw.addr; - *cs_base =3D 0; + *cs_base =3D env->ex_value; *flags =3D ((env->psw.mask >> 32) & ~FLAG_MASK_CC) | ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0); } diff --git a/target/s390x/helper.c b/target/s390x/helper.c index 9978490..f01811f 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -642,6 +642,11 @@ bool s390_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) S390CPU *cpu =3D S390_CPU(cs); CPUS390XState *env =3D &cpu->env; =20 + if (env->ex_value) { + /* Execution of the target insn is indivisible from + the parent EXECUTE insn. */ + return false; + } if (env->psw.mask & PSW_MASK_EXT) { s390_cpu_do_interrupt(cs); return true; diff --git a/target/s390x/machine.c b/target/s390x/machine.c index 8503fa1..8f908bb 100644 --- a/target/s390x/machine.c +++ b/target/s390x/machine.c @@ -34,6 +34,7 @@ static int cpu_post_load(void *opaque, int version_id) =20 return 0; } + static void cpu_pre_save(void *opaque) { S390CPU *cpu =3D opaque; @@ -156,6 +157,23 @@ const VMStateDescription vmstate_riccb =3D { } }; =20 +static bool exval_needed(void *opaque) +{ + S390CPU *cpu =3D opaque; + return cpu->env.ex_value !=3D 0; +} + +const VMStateDescription vmstate_exval =3D { + .name =3D "cpu/exval", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D exval_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.ex_value, S390CPU), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_s390_cpu =3D { .name =3D "cpu", .post_load =3D cpu_post_load, @@ -188,6 +206,7 @@ const VMStateDescription vmstate_s390_cpu =3D { &vmstate_fpu, &vmstate_vregs, &vmstate_riccb, + &vmstate_exval, NULL }, }; diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index d57d5b1..3a77edc 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -435,37 +435,6 @@ uint64_t HELPER(mvst)(CPUS390XState *env, uint64_t c, = uint64_t d, uint64_t s) return d + len; } =20 -static uint32_t helper_icm(CPUS390XState *env, uint32_t r1, uint64_t addre= ss, - uint32_t mask) -{ - int pos =3D 24; /* top of the lower half of r1 */ - uint64_t rmask =3D 0xff000000ULL; - uint8_t val =3D 0; - int ccd =3D 0; - uint32_t cc =3D 0; - - while (mask) { - if (mask & 8) { - env->regs[r1] &=3D ~rmask; - val =3D cpu_ldub_data(env, address); - if ((val & 0x80) && !ccd) { - cc =3D 1; - } - ccd =3D 1; - if (val && cc =3D=3D 0) { - cc =3D 2; - } - env->regs[r1] |=3D (uint64_t)val << pos; - address++; - } - mask =3D (mask << 1) & 0xf; - pos -=3D 8; - rmask >>=3D 8; - } - - return cc; -} - /* load access registers r1 to r3 from memory at a2 */ void HELPER(lam)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) { @@ -1222,19 +1191,17 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t a= ddr) } #endif =20 -/* execute instruction - this instruction executes an insn modified with the contents of r1 - it does not change the executed instruction in memory - it does not change the program counter - in other words: tricky... - currently implemented by interpreting the cases it is most commonly use= d. +/* Execute instruction. This instruction executes an insn modified with + the contents of r1. It does not change the executed instruction in mem= ory; + it does not change the program counter. + + Perform this by recording the modified instruction in env->ex_value. + This will be noticed by cpu_get_tb_cpu_state and thus tb translation. */ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, uint64_t r1, uint64_t a= ddr) { - S390CPU *cpu =3D s390_env_get_cpu(env); uint64_t insn =3D cpu_lduw_code(env, addr); uint8_t opc =3D insn >> 8; - uint32_t cc; =20 /* Or in the contents of R1[56:63]. */ insn |=3D r1 & 0xff; @@ -1254,72 +1221,9 @@ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, u= int64_t r1, uint64_t addr) g_assert_not_reached(); } =20 - HELPER_LOG("%s: addr 0x%lx insn 0x%" PRIx64 "\n", __func__, addr, insn= ); - - if ((opc & 0xf0) =3D=3D 0xd0) { - uint32_t l, b1, b2, d1, d2; - - l =3D extract64(insn, 48, 8); - b1 =3D extract64(insn, 44, 4); - b2 =3D extract64(insn, 28, 4); - d1 =3D extract64(insn, 32, 12); - d2 =3D extract64(insn, 16, 12); - - cc =3D env->cc_op; - switch (opc & 0xf) { - case 0x2: - do_helper_mvc(env, l, get_address(env, 0, b1, d1), - get_address(env, 0, b2, d2), 0); - break; - case 0x4: - cc =3D do_helper_nc(env, l, get_address(env, 0, b1, d1), - get_address(env, 0, b2, d2), 0); - break; - case 0x5: - cc =3D do_helper_clc(env, l, get_address(env, 0, b1, d1), - get_address(env, 0, b2, d2), 0); - break; - case 0x6: - cc =3D do_helper_oc(env, l, get_address(env, 0, b1, d1), - get_address(env, 0, b2, d2), 0); - break; - case 0x7: - cc =3D do_helper_xc(env, l, get_address(env, 0, b1, d1), - get_address(env, 0, b2, d2), 0); - break; - case 0xc: - do_helper_tr(env, l, get_address(env, 0, b1, d1), - get_address(env, 0, b2, d2), 0); - break; - case 0xd: - cc =3D do_helper_trt(env, l, get_address(env, 0, b1, d1), - get_address(env, 0, b2, d2), 0); - break; - default: - goto abort; - } - } else if (opc =3D=3D 0x0a) { - /* supervisor call */ - env->int_svc_code =3D extract64(insn, 48, 8); - env->int_svc_ilen =3D ilen; - helper_exception(env, EXCP_SVC); - g_assert_not_reached(); - } else if (opc =3D=3D 0xbf) { - uint32_t r1, r3, b2, d2; - - r1 =3D extract64(insn, 52, 4); - r3 =3D extract64(insn, 48, 4); - b2 =3D extract64(insn, 44, 4); - d2 =3D extract64(insn, 32, 12); - cc =3D helper_icm(env, r1, get_address(env, 0, b2, d2), r3); - } else { - abort: - cpu_abort(CPU(cpu), - "EXECUTE on instruction prefix 0x%x not implemented\n", - opc); - g_assert_not_reached(); - } - - env->cc_op =3D cc; - env->psw.addr +=3D ilen; + /* Record the insn we want to execute as well as the ilen to use + during the execution of the target insn. This will also ensure + that ex_value is non-zero, which flags that we are in a state + that requires such execution. */ + env->ex_value =3D insn | ilen; } diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 70212c8..97ca639 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -57,6 +57,7 @@ struct DisasContext { struct TranslationBlock *tb; const DisasInsn *insn; DisasFields *fields; + uint64_t ex_value; uint64_t pc, next_pc; uint32_t ilen; enum cc_op cc_op; @@ -2186,23 +2187,18 @@ static ExitStatus op_epsw(DisasContext *s, DisasOps= *o) =20 static ExitStatus op_ex(DisasContext *s, DisasOps *o) { - /* ??? Perhaps a better way to implement EXECUTE is to set a bit in - tb->flags, (ab)use the tb->cs_base field as the address of - the template in memory, and grab 8 bits of tb->flags/cflags for - the contents of the register. We would then recognize all this - in gen_intermediate_code_internal, generating code for exactly - one instruction. This new TB then gets executed normally. - - On the other hand, this seems to be mostly used for modifying - MVC inside of memcpy, which needs a helper call anyway. So - perhaps this doesn't bear thinking about any further. */ - int r1 =3D get_field(s->fields, r1); TCGv_i32 ilen; TCGv_i64 v1; =20 + /* Nested EXECUTE is not allowed. */ + if (unlikely(s->ex_value)) { + gen_program_exception(s, PGM_EXECUTE); + return EXIT_NORETURN; + } + update_psw_addr(s); - gen_op_calc_cc(s); + update_cc_op(s); =20 if (r1 =3D=3D 0) { v1 =3D tcg_const_i64(0); @@ -5190,25 +5186,36 @@ static const DisasInsn *extract_insn(CPUS390XState = *env, DisasContext *s, int op, op2, ilen; const DisasInsn *info; =20 - insn =3D ld_code2(env, pc); - op =3D (insn >> 8) & 0xff; - ilen =3D get_ilen(op); - s->next_pc =3D s->pc + ilen; - s->ilen =3D ilen; + if (unlikely(s->ex_value)) { + /* Drop the EX data now, so that it's clear on exception paths. */ + TCGv_i64 zero =3D tcg_const_i64(0); + tcg_gen_st_i64(zero, cpu_env, offsetof(CPUS390XState, ex_value)); + tcg_temp_free_i64(zero); =20 - switch (ilen) { - case 2: - insn =3D insn << 48; - break; - case 4: - insn =3D ld_code4(env, pc) << 32; - break; - case 6: - insn =3D (insn << 48) | (ld_code4(env, pc + 2) << 16); - break; - default: - abort(); + /* Extract the values saved by EXECUTE. */ + insn =3D s->ex_value & 0xffffffffffff0000ull; + ilen =3D s->ex_value & 0xf; + op =3D insn >> 56; + } else { + insn =3D ld_code2(env, pc); + op =3D (insn >> 8) & 0xff; + ilen =3D get_ilen(op); + switch (ilen) { + case 2: + insn =3D insn << 48; + break; + case 4: + insn =3D ld_code4(env, pc) << 32; + break; + case 6: + insn =3D (insn << 48) | (ld_code4(env, pc + 2) << 16); + break; + default: + g_assert_not_reached(); + } } + s->next_pc =3D s->pc + ilen; + s->ilen =3D ilen; =20 /* We can't actually determine the insn format until we've looked up the full insn opcode. Which we can't do without locating the @@ -5425,6 +5432,7 @@ void gen_intermediate_code(CPUS390XState *env, struct= TranslationBlock *tb) dc.tb =3D tb; dc.pc =3D pc_start; dc.cc_op =3D CC_OP_DYNAMIC; + dc.ex_value =3D tb->cs_base; do_debug =3D dc.singlestep_enabled =3D cs->singlestep_enabled; =20 next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; @@ -5471,7 +5479,8 @@ void gen_intermediate_code(CPUS390XState *env, struct= TranslationBlock *tb) || tcg_op_buf_full() || num_insns >=3D max_insns || singlestep - || cs->singlestep_enabled)) { + || cs->singlestep_enabled + || dc.ex_value)) { status =3D EXIT_PC_STALE; } } while (status =3D=3D NO_EXIT); @@ -5513,9 +5522,14 @@ void gen_intermediate_code(CPUS390XState *env, struc= t TranslationBlock *tb) if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && qemu_log_in_addr_range(pc_start)) { qemu_log_lock(); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc.pc - pc_start, 1); - qemu_log("\n"); + if (unlikely(dc.ex_value)) { + /* ??? Unfortunately log_target_disas can't use host memory. = */ + qemu_log("IN: EXECUTE %016" PRIx64 "\n", dc.ex_value); + } else { + qemu_log("IN: %s\n", lookup_symbol(pc_start)); + log_target_disas(cs, pc_start, dc.pc - pc_start, 1); + qemu_log("\n"); + } qemu_log_unlock(); } #endif --=20 2.9.4 From nobody Tue Apr 30 01:16:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1495663903865114.52766018118473; Wed, 24 May 2017 15:11:43 -0700 (PDT) Received: from localhost ([::1]:57036 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dDeVJ-0001a5-Q0 for importer@patchew.org; Wed, 24 May 2017 18:11:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57366) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dDeSP-0007gU-3B for qemu-devel@nongnu.org; Wed, 24 May 2017 18:08:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dDeSN-00059h-To for qemu-devel@nongnu.org; Wed, 24 May 2017 18:08:41 -0400 Received: from mail-qt0-x244.google.com ([2607:f8b0:400d:c0d::244]:33354) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dDeSN-00059V-OW for qemu-devel@nongnu.org; Wed, 24 May 2017 18:08:39 -0400 Received: by mail-qt0-x244.google.com with SMTP id a46so28076333qte.0 for ; Wed, 24 May 2017 15:08:39 -0700 (PDT) Received: from bigtime.twiddle.net.com ([2602:47:d954:1500:5e51:4fff:fe40:9c64]) by smtp.gmail.com with ESMTPSA id y188sm3347693qkb.49.2017.05.24.15.08.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 24 May 2017 15:08:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=10kBqtvYA3p+2fUWkIT0DQhdw93yxtXRcMkzzIh8YuQ=; b=n7p5ZeSFwlXyaJbDgtIX1eMRvuxeQrwPjzdz3X4nKU2olzWSo97+7mjGh/ioyxBWa7 n3zUL8MowuqEvWKBky5sW3GIU+VdnMMBYAoOgRk4sMjeRbfQUfMmH70z9pd3Qc2fpZHJ tmwGK33ajzU/T0OirA9u70ltMfeF4rtAMCSkK4p7Zav5y8QXWJnf6AeyouP9l4UN18ol DzowYgTDFvOn9f3cNeIsVsH26Vj/9IAoBpJZRF+v3o4RpQzadkqWsUgYjGf/OR5qY+YQ eHarFTRgE1ZT4YclVHo2PUhpUasb+JflM5mCzix7dQwXkRiFJFjJFqVup6ZrX4Dmkkwl bIJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=10kBqtvYA3p+2fUWkIT0DQhdw93yxtXRcMkzzIh8YuQ=; b=Fc4PyBQlsh5KyGucfMUldpLx02iPwP3nQUVTafh22G+ppjLvL3aQpo4kJYs9HF9WkG WX8kRuVoMF9xMBJFV89G03zXjyPB5fYQP2QkF5BlsAHRxP4XGTFkRowcyGUUZutGaHN1 aYrWlhEFT8veh02NC/IQLwls9+rAl46rJicPxZSf/puMqJpermw3ddKbcKzxTtTUIpBo wYsPbMHQEnUMJkpZ6DidEXxIHqIkv4FqraK8Hnsl1L+ajdjffRZQ9aPOyZ+smxEGkT7v ybG+v0H9U/NzgNXEb8viRwPUOzJMvA2twtVr6f9Vd/u9hcW9HmgaX4NJ4ctWB5t2qYmh tJVQ== X-Gm-Message-State: AODbwcBUCt61LwortfG1ovP1r0u8Oe1blL13QAUcj6Fyk8YednKm+QQI mShJizaiEFHI2oICOYU= X-Received: by 10.237.37.154 with SMTP id x26mr39654140qtc.133.1495663719041; Wed, 24 May 2017 15:08:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 May 2017 15:08:27 -0700 Message-Id: <20170524220827.21154-5-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170524220827.21154-1-rth@twiddle.net> References: <20170524220827.21154-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::244 Subject: [Qemu-devel] [PATCH 4/4] target/s390x: Re-implement a few EXECUTE target insns directly X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" While the previous patch is required for proper conformance, the vast majority of target insns are MVC and XC for implementing memmove and memset respectively. The next most common are CLC, TR, and SVC. Implementing these (and a few others for which we already have an implementation) directly is faster than going through full translation to a TB. Signed-off-by: Richard Henderson Reviewed-by: Aurelien Jarno --- target/s390x/mem_helper.c | 66 ++++++++++++++++++++++++++++++++++++-------= ---- 1 file changed, 51 insertions(+), 15 deletions(-) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 3a77edc..e35571e 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -200,31 +200,30 @@ uint32_t HELPER(oc)(CPUS390XState *env, uint32_t l, u= int64_t dest, } =20 /* memmove */ -static void do_helper_mvc(CPUS390XState *env, uint32_t l, uint64_t dest, - uint64_t src, uintptr_t ra) +static uint32_t do_helper_mvc(CPUS390XState *env, uint32_t l, uint64_t des= t, + uint64_t src, uintptr_t ra) { uint32_t i; =20 HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n", __func__, l, dest, src); =20 + /* mvc and memmove do not behave the same when areas overlap! */ /* mvc with source pointing to the byte after the destination is the same as memset with the first source byte */ if (dest =3D=3D src + 1) { fast_memset(env, dest, cpu_ldub_data_ra(env, src, ra), l + 1, ra); - return; - } - - /* mvc and memmove do not behave the same when areas overlap! */ - if (dest < src || src + l < dest) { + } else if (dest < src || src + l < dest) { fast_memmove(env, dest, src, l + 1, ra); - return; + } else { + /* slow version with byte accesses which always work */ + for (i =3D 0; i <=3D l; i++) { + uint8_t x =3D cpu_ldub_data_ra(env, src + i, ra); + cpu_stb_data_ra(env, dest + i, x, ra); + } } =20 - /* slow version with byte accesses which always work */ - for (i =3D 0; i <=3D l; i++) { - cpu_stb_data_ra(env, dest + i, cpu_ldub_data_ra(env, src + i, ra),= ra); - } + return env->cc_op; } =20 void HELPER(mvc)(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t s= rc) @@ -692,8 +691,8 @@ void HELPER(unpk)(CPUS390XState *env, uint32_t len, uin= t64_t dest, } } =20 -static void do_helper_tr(CPUS390XState *env, uint32_t len, uint64_t array, - uint64_t trans, uintptr_t ra) +static uint32_t do_helper_tr(CPUS390XState *env, uint32_t len, uint64_t ar= ray, + uint64_t trans, uintptr_t ra) { uint32_t i; =20 @@ -702,12 +701,14 @@ static void do_helper_tr(CPUS390XState *env, uint32_t= len, uint64_t array, uint8_t new_byte =3D cpu_ldub_data_ra(env, trans + byte, ra); cpu_stb_data_ra(env, array + i, new_byte, ra); } + + return env->cc_op; } =20 void HELPER(tr)(CPUS390XState *env, uint32_t len, uint64_t array, uint64_t trans) { - return do_helper_tr(env, len, array, trans, GETPC()); + do_helper_tr(env, len, array, trans, GETPC()); } =20 uint64_t HELPER(tre)(CPUS390XState *env, uint64_t array, @@ -1221,6 +1222,41 @@ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, u= int64_t r1, uint64_t addr) g_assert_not_reached(); } =20 + /* The very most common cases can be sped up by avoiding a new TB. */ + if ((opc & 0xf0) =3D=3D 0xd0) { + typedef uint32_t (*dx_helper)(CPUS390XState *, uint32_t, uint64_t, + uint64_t, uintptr_t); + static const dx_helper dx[16] =3D { + [0x2] =3D do_helper_mvc, + [0x4] =3D do_helper_nc, + [0x5] =3D do_helper_clc, + [0x6] =3D do_helper_oc, + [0x7] =3D do_helper_xc, + [0xc] =3D do_helper_tr, + [0xd] =3D do_helper_trt, + }; + dx_helper helper =3D dx[opc & 0xf]; + + if (helper) { + uint32_t l =3D extract64(insn, 48, 8); + uint32_t b1 =3D extract64(insn, 44, 4); + uint32_t d1 =3D extract64(insn, 32, 12); + uint32_t b2 =3D extract64(insn, 28, 4); + uint32_t d2 =3D extract64(insn, 16, 12); + uint64_t a1 =3D get_address(env, 0, b1, d1); + uint64_t a2 =3D get_address(env, 0, b2, d2); + + env->cc_op =3D helper(env, l, a1, a2, 0); + env->psw.addr +=3D ilen; + return; + } + } else if (opc =3D=3D 0x0a) { + env->int_svc_code =3D extract64(insn, 48, 8); + env->int_svc_ilen =3D ilen; + helper_exception(env, EXCP_SVC); + g_assert_not_reached(); + } + /* Record the insn we want to execute as well as the ilen to use during the execution of the target insn. This will also ensure that ex_value is non-zero, which flags that we are in a state --=20 2.9.4