From nobody Mon Feb 9 08:55:16 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1494976027705138.40364116268427; Tue, 16 May 2017 16:07:07 -0700 (PDT) Received: from localhost ([::1]:44510 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dAlYY-0002au-E6 for importer@patchew.org; Tue, 16 May 2017 19:07:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50527) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dAlTo-0007yL-67 for qemu-devel@nongnu.org; Tue, 16 May 2017 19:02:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dAlTn-0002dn-7v for qemu-devel@nongnu.org; Tue, 16 May 2017 19:02:12 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:45190) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dAlTn-0002dA-35; Tue, 16 May 2017 19:02:11 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1dAlTk-00021L-C0; Wed, 17 May 2017 01:02:08 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1dAlTj-00022A-Ja; Wed, 17 May 2017 01:02:07 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Wed, 17 May 2017 01:01:57 +0200 Message-Id: <20170516230159.4195-3-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170516230159.4195-1-aurelien@aurel32.net> References: <20170516230159.4195-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PATCH 2/4] target/arm: simplify and optimize aarch64 rev16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "open list:ARM" , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Instead of byteswapping individual 16-bit words one by one, work on the whole register at the same time using shifts and mask. This is the same strategy than the aarch32 version of rev16 and is much more efficient in the case sf=3D1. Signed-off-by: Aurelien Jarno Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 24 ++++++------------------ 1 file changed, 6 insertions(+), 18 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 24de30d92c..ed15d21655 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4035,24 +4035,12 @@ static void handle_rev16(DisasContext *s, unsigned = int sf, TCGv_i64 tcg_tmp =3D tcg_temp_new_i64(); TCGv_i64 tcg_rn =3D read_cpu_reg(s, rn, sf); =20 - tcg_gen_andi_i64(tcg_tmp, tcg_rn, 0xffff); - tcg_gen_bswap16_i64(tcg_rd, tcg_tmp); - - tcg_gen_shri_i64(tcg_tmp, tcg_rn, 16); - tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff); - tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); - tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 16, 16); - - if (sf) { - tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32); - tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff); - tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); - tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 32, 16); - - tcg_gen_shri_i64(tcg_tmp, tcg_rn, 48); - tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); - tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 48, 16); - } + TCGv mask =3D tcg_const_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff); + tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8); + tcg_gen_and_i64(tcg_rd, tcg_rn, mask); + tcg_gen_and_i64(tcg_tmp, tcg_tmp, mask); + tcg_gen_shli_i64(tcg_rd, tcg_rd, 8); + tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp); =20 tcg_temp_free_i64(tcg_tmp); } --=20 2.11.0