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X-Received-From: 2607:f8b0:400d:c09::241 Subject: [Qemu-devel] [PATCH v2 5/6] target/s390x: Use atomic operations for COMPARE SWAP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Aurelien Jarno --- target/s390x/helper.h | 1 + target/s390x/mem_helper.c | 39 ++++++++++++++++++++++ target/s390x/translate.c | 83 +++++++++----------------------------------= ---- 3 files changed, 55 insertions(+), 68 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 01adb50..0b70770 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -25,6 +25,7 @@ DEF_HELPER_3(cxgb, i64, env, s64, i32) DEF_HELPER_3(celgb, i64, env, i64, i32) DEF_HELPER_3(cdlgb, i64, env, i64, i32) DEF_HELPER_3(cxlgb, i64, env, i64, i32) +DEF_HELPER_4(cdsg, void, env, i64, i32, i32) DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(adb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_5(axb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 675aba2..c74ded3 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -844,6 +844,45 @@ uint32_t HELPER(trt)(CPUS390XState *env, uint32_t len,= uint64_t array, return cc; } =20 +void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, + uint32_t r1, uint32_t r3) +{ + uintptr_t ra =3D GETPC(); + Int128 cmpv =3D int128_make128(env->regs[r1 + 1], env->regs[r1]); + Int128 newv =3D int128_make128(env->regs[r3 + 1], env->regs[r3]); + int mem_idx =3D cpu_mmu_index(env, false); + Int128 oldv; + bool fail; + + if (parallel_cpus) { +#ifndef CONFIG_ATOMIC128 + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); +#else + TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, = ra); + fail =3D !int128_eq(oldv, cmpv); +#endif + } else { + uint64_t oldh, oldl; + + oldh =3D cpu_ldq_data_ra(env, addr + 0, ra); + oldl =3D cpu_ldq_data_ra(env, addr + 8, ra); + + oldv =3D int128_make128(oldl, oldh); + fail =3D !int128_eq(oldv, cmpv); + if (fail) { + newv =3D oldv; + } + + cpu_stq_data_ra(env, addr + 0, int128_gethi(newv), ra); + cpu_stq_data_ra(env, addr + 8, int128_getlo(newv), ra); + } + + env->cc_op =3D fail; + env->regs[r1] =3D int128_gethi(oldv); + env->regs[r1 + 1] =3D int128_getlo(oldv); +} + #if !defined(CONFIG_USER_ONLY) void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t = r3) { diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 8de0177..414378c 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -1943,102 +1943,49 @@ static ExitStatus op_cps(DisasContext *s, DisasOps= *o) =20 static ExitStatus op_cs(DisasContext *s, DisasOps *o) { - /* FIXME: needs an atomic solution for CONFIG_USER_ONLY. */ int d2 =3D get_field(s->fields, d2); int b2 =3D get_field(s->fields, b2); int is_64 =3D s->insn->data; - TCGv_i64 addr, mem, cc, z; + TCGv_i64 addr, cc; =20 /* Note that in1 =3D R3 (new value) and in2 =3D (zero-extended) R1 (expected value). */ =20 - /* Load the memory into the (temporary) output. While the PoO only ta= lks - about moving the memory to R1 on inequality, if we include equality= it - means that R1 is equal to the memory in all conditions. */ addr =3D get_address(s, 0, b2, d2); - if (is_64) { - tcg_gen_qemu_ld64(o->out, addr, get_mem_index(s)); - } else { - tcg_gen_qemu_ld32u(o->out, addr, get_mem_index(s)); - } + tcg_gen_atomic_cmpxchg_i64(o->out, addr, o->in2, o->in1, + get_mem_index(s), + (is_64 ? MO_TEQ : MO_TEUL) | MO_ALIGN); + tcg_temp_free_i64(addr); =20 /* Are the memory and expected values (un)equal? Note that this setco= nd produces the output CC value, thus the NE sense of the test. */ cc =3D tcg_temp_new_i64(); tcg_gen_setcond_i64(TCG_COND_NE, cc, o->in2, o->out); - - /* If the memory and expected values are equal (CC=3D=3D0), copy R3 to= MEM. - Recall that we are allowed to unconditionally issue the store (and - thus any possible write trap), so (re-)store the original contents - of MEM in case of inequality. */ - z =3D tcg_const_i64(0); - mem =3D tcg_temp_new_i64(); - tcg_gen_movcond_i64(TCG_COND_EQ, mem, cc, z, o->in1, o->out); - if (is_64) { - tcg_gen_qemu_st64(mem, addr, get_mem_index(s)); - } else { - tcg_gen_qemu_st32(mem, addr, get_mem_index(s)); - } - tcg_temp_free_i64(z); - tcg_temp_free_i64(mem); - tcg_temp_free_i64(addr); - - /* Store CC back to cc_op. Wait until after the store so that any - exception gets the old cc_op value. */ tcg_gen_extrl_i64_i32(cc_op, cc); tcg_temp_free_i64(cc); set_cc_static(s); + return NO_EXIT; } =20 static ExitStatus op_cdsg(DisasContext *s, DisasOps *o) { - /* FIXME: needs an atomic solution for CONFIG_USER_ONLY. */ int r1 =3D get_field(s->fields, r1); int r3 =3D get_field(s->fields, r3); int d2 =3D get_field(s->fields, d2); int b2 =3D get_field(s->fields, b2); - TCGv_i64 addrh, addrl, memh, meml, outh, outl, cc, z; + TCGv_i64 addr; + TCGv_i32 t_r1, t_r3; =20 /* Note that R1:R1+1 =3D expected value and R3:R3+1 =3D new value. */ + addr =3D get_address(s, 0, b2, d2); + t_r1 =3D tcg_const_i32(r1); + t_r3 =3D tcg_const_i32(r3); + gen_helper_cdsg(cpu_env, addr, t_r1, t_r3); + tcg_temp_free_i64(addr); + tcg_temp_free_i32(t_r1); + tcg_temp_free_i32(t_r3); =20 - addrh =3D get_address(s, 0, b2, d2); - addrl =3D get_address(s, 0, b2, d2 + 8); - outh =3D tcg_temp_new_i64(); - outl =3D tcg_temp_new_i64(); - - tcg_gen_qemu_ld64(outh, addrh, get_mem_index(s)); - tcg_gen_qemu_ld64(outl, addrl, get_mem_index(s)); - - /* Fold the double-word compare with arithmetic. */ - cc =3D tcg_temp_new_i64(); - z =3D tcg_temp_new_i64(); - tcg_gen_xor_i64(cc, outh, regs[r1]); - tcg_gen_xor_i64(z, outl, regs[r1 + 1]); - tcg_gen_or_i64(cc, cc, z); - tcg_gen_movi_i64(z, 0); - tcg_gen_setcond_i64(TCG_COND_NE, cc, cc, z); - - memh =3D tcg_temp_new_i64(); - meml =3D tcg_temp_new_i64(); - tcg_gen_movcond_i64(TCG_COND_EQ, memh, cc, z, regs[r3], outh); - tcg_gen_movcond_i64(TCG_COND_EQ, meml, cc, z, regs[r3 + 1], outl); - tcg_temp_free_i64(z); - - tcg_gen_qemu_st64(memh, addrh, get_mem_index(s)); - tcg_gen_qemu_st64(meml, addrl, get_mem_index(s)); - tcg_temp_free_i64(memh); - tcg_temp_free_i64(meml); - tcg_temp_free_i64(addrh); - tcg_temp_free_i64(addrl); - - /* Save back state now that we've passed all exceptions. */ - tcg_gen_mov_i64(regs[r1], outh); - tcg_gen_mov_i64(regs[r1 + 1], outl); - tcg_gen_extrl_i64_i32(cc_op, cc); - tcg_temp_free_i64(outh); - tcg_temp_free_i64(outl); - tcg_temp_free_i64(cc); set_cc_static(s); return NO_EXIT; } --=20 2.9.3