From nobody Mon Feb 9 23:00:19 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1494069859610379.1013885360105; Sat, 6 May 2017 04:24:19 -0700 (PDT) Received: from localhost ([::1]:50934 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d6xov-0002o4-7t for importer@patchew.org; Sat, 06 May 2017 07:24:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50913) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d6xfh-00030k-73 for qemu-devel@nongnu.org; Sat, 06 May 2017 07:14:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d6xff-0003vs-2i for qemu-devel@nongnu.org; Sat, 06 May 2017 07:14:45 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:40012) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d6xfe-0003uO-QR for qemu-devel@nongnu.org; Sat, 06 May 2017 07:14:42 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1d6xfd-0008N8-H5; Sat, 06 May 2017 13:14:41 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1d6xfc-0003IZ-4c; Sat, 06 May 2017 13:14:40 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sat, 6 May 2017 13:14:31 +0200 Message-Id: <20170506111431.12548-15-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170506111431.12548-1-aurelien@aurel32.net> References: <20170506111431.12548-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PATCH v2 14/14] target/sh4: trap unaligned accesses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 SH4 requires that memory accesses are naturally aligned, except for the SH4-A movua.l instructions which can do unaligned loads. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson --- target/sh4/cpu.c | 1 + target/sh4/cpu.h | 4 ++++ target/sh4/op_helper.c | 19 +++++++++++++++++++ target/sh4/translate.c | 6 ++++-- 4 files changed, 28 insertions(+), 2 deletions(-) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 9a481c35dc..9da7e1ed38 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -301,6 +301,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault =3D superh_cpu_handle_mmu_fault; #else + cc->do_unaligned_access =3D superh_cpu_do_unaligned_access; cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D superh_cpu_disas_set_info; diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index faab3012f9..6c07c6b24b 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -24,6 +24,7 @@ #include "cpu-qom.h" =20 #define TARGET_LONG_BITS 32 +#define ALIGNED_ONLY =20 /* CPU Subtypes */ #define SH_CPU_SH7750 (1 << 0) @@ -215,6 +216,9 @@ void superh_cpu_dump_state(CPUState *cpu, FILE *f, hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int superh_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); =20 void sh4_translate_init(void); SuperHCPU *cpu_sh4_init(const char *cpu_model); diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 684d3f3758..4abd05667c 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -24,6 +24,25 @@ =20 #ifndef CONFIG_USER_ONLY =20 +void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + if (retaddr) { + cpu_restore_state(cs, retaddr); + } + switch (access_type) { + case MMU_INST_FETCH: + case MMU_DATA_LOAD: + cs->exception_index =3D 0x0e0; + break; + case MMU_DATA_STORE: + cs->exception_index =3D 0x100; + break; + } + cpu_loop_exit(cs); +} + void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 29ea506c1d..e4e602021e 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1505,14 +1505,16 @@ static void _decode_opc(DisasContext * ctx) case 0x40a9: /* movua.l @Rm,R0 */ /* Load non-boundary-aligned data */ if (ctx->features & SH_FEATURE_SH4A) { - tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL); + tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, + MO_TEUL | MO_UNALN); return; } break; case 0x40e9: /* movua.l @Rm+,R0 */ /* Load non-boundary-aligned data */ if (ctx->features & SH_FEATURE_SH4A) { - tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL); + tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, + MO_TEUL | MO_UNALN); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); return; } --=20 2.11.0