From nobody Mon Feb 9 03:46:23 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493979326556885.3603882116213; Fri, 5 May 2017 03:15:26 -0700 (PDT) Received: from localhost ([::1]:46041 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d6aGj-0003N1-4V for importer@patchew.org; Fri, 05 May 2017 06:15:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46999) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d6aF6-0002CN-KP for qemu-devel@nongnu.org; Fri, 05 May 2017 06:13:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d6aF5-0006ai-0M for qemu-devel@nongnu.org; Fri, 05 May 2017 06:13:44 -0400 Received: from mx1.redhat.com ([209.132.183.28]:41670) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d6aF4-0006aV-QB for qemu-devel@nongnu.org; Fri, 05 May 2017 06:13:42 -0400 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id D12CA81229; Fri, 5 May 2017 10:13:41 +0000 (UTC) Received: from donizetti.redhat.com (ovpn-116-145.ams2.redhat.com [10.36.116.145]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id v45ADbkJ026855; Fri, 5 May 2017 06:13:41 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com D12CA81229 Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=pbonzini@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com D12CA81229 From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Fri, 5 May 2017 12:13:18 +0200 Message-Id: <20170505101337.4650-3-pbonzini@redhat.com> In-Reply-To: <20170505101337.4650-1-pbonzini@redhat.com> References: <20170505101337.4650-1-pbonzini@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Fri, 05 May 2017 10:13:42 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 02/21] hw/i386: Build-time assertion on pc/q35 reset register being identical. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Phil Dennis-Jordan Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Phil Dennis-Jordan This adds a clarifying comment and build time assert to the FADT reset regi= ster field initialisation: the reset register is the same on both machine t= ypes. Signed-off-by: Phil Dennis-Jordan Message-Id: <1489558827-28971-3-git-send-email-phil@philjordan.eu> Signed-off-by: Paolo Bonzini --- hw/i386/acpi-build.c | 3 +++ hw/pci-host/piix.c | 6 ------ include/hw/i386/pc.h | 6 ++++++ 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 7997f06823..1d8c645ed3 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -310,6 +310,9 @@ static void fadt_setup(AcpiFadtDescriptorRev3 *fadt, Ac= piPmInfo *pm) fadt->reset_register.space_id =3D AML_SYSTEM_IO; fadt->reset_register.bit_width =3D 8; fadt->reset_register.address =3D cpu_to_le64(ICH9_RST_CNT_IOPORT); + /* The above need not be conditional on machine type because the reset= port + * happens to be the same on PIIX (pc) and ICH9 (q35). */ + QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT !=3D RCR_IOPORT); =20 fadt->xpm1a_event_block.space_id =3D AML_SYSTEM_IO; fadt->xpm1a_event_block.bit_width =3D fadt->pm1_evt_len * 8; diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index f9218aa952..bf4221d4bf 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -58,12 +58,6 @@ typedef struct I440FXState { #define XEN_PIIX_NUM_PIRQS 128ULL #define PIIX_PIRQC 0x60 =20 -/* - * Reset Control Register: PCI-accessible ISA-Compatible Register at addre= ss - * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). - */ -#define RCR_IOPORT 0xcf9 - typedef struct PIIX3State { PCIDevice dev; =20 diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index f278b3ae89..416aaa56ea 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -303,6 +303,12 @@ typedef struct PCII440FXState PCII440FXState; =20 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX" =20 +/* + * Reset Control Register: PCI-accessible ISA-Compatible Register at addre= ss + * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). + */ +#define RCR_IOPORT 0xcf9 + PCIBus *i440fx_init(const char *host_type, const char *pci_type, PCII440FXState **pi440fx_state, int *piix_devfn, ISABus **isa_bus, qemu_irq *pic, --=20 2.12.2