From nobody Mon Feb 9 10:48:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493676785060181.6045102177078; Mon, 1 May 2017 15:13:05 -0700 (PDT) Received: from localhost ([::1]:55928 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d5JZ1-0000Rb-EN for importer@patchew.org; Mon, 01 May 2017 18:13:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45843) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d5JX4-0007YI-Rg for qemu-devel@nongnu.org; Mon, 01 May 2017 18:11:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d5JX3-0004G6-AS for qemu-devel@nongnu.org; Mon, 01 May 2017 18:11:02 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:57328) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d5JX3-0004Bf-3c for qemu-devel@nongnu.org; Mon, 01 May 2017 18:11:01 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1d5JWu-00039n-AD; Tue, 02 May 2017 00:10:52 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1d5JWs-0002pT-TF; Tue, 02 May 2017 00:10:50 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Tue, 2 May 2017 00:10:42 +0200 Message-Id: <20170501221046.9369-11-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170501221046.9369-1-aurelien@aurel32.net> References: <20170501221046.9369-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PATCH 10/14] target/sh4: optimize gen_write_sr using extract op X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This doesn't change the generated code on x86, but optimizes it on most RISC architectures and makes the code simpler to read. Signed-off-by: Aurelien Jarno --- target/sh4/translate.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 23636eeb4c..7de459c9a5 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -204,12 +204,9 @@ static void gen_write_sr(TCGv src) { tcg_gen_andi_i32(cpu_sr, src, ~((1u << SR_Q) | (1u << SR_M) | (1u << SR_T))); - tcg_gen_shri_i32(cpu_sr_q, src, SR_Q); - tcg_gen_andi_i32(cpu_sr_q, cpu_sr_q, 1); - tcg_gen_shri_i32(cpu_sr_m, src, SR_M); - tcg_gen_andi_i32(cpu_sr_m, cpu_sr_m, 1); - tcg_gen_shri_i32(cpu_sr_t, src, SR_T); - tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1); + tcg_gen_extract_i32(cpu_sr_q, src, SR_Q, 1); + tcg_gen_extract_i32(cpu_sr_m, src, SR_M, 1); + tcg_gen_extract_i32(cpu_sr_t, src, SR_T, 1); } =20 static inline void gen_save_cpu_state(DisasContext *ctx, bool save_pc) --=20 2.11.0