From nobody Sun Apr 28 11:28:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493386986132152.39636524249408; Fri, 28 Apr 2017 06:43:06 -0700 (PDT) Received: from localhost ([::1]:37178 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d46Ap-0002jj-Ar for importer@patchew.org; Fri, 28 Apr 2017 09:43:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48008) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d45Sa-0005Ox-1j for qemu-devel@nongnu.org; Fri, 28 Apr 2017 08:57:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d45SU-0001Fn-JY for qemu-devel@nongnu.org; Fri, 28 Apr 2017 08:57:20 -0400 Received: from bee.antfield.fr ([188.165.75.195]:54724) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d45SO-0001Bl-7O; Fri, 28 Apr 2017 08:57:08 -0400 From: Luc MICHEL To: qemu-devel@nongnu.org Date: Fri, 28 Apr 2017 14:56:32 +0200 Message-Id: <20170428125632.5704-2-luc.michel@git.antfield.fr> X-Mailer: git-send-email 2.12.2 In-Reply-To: <20170428125632.5704-1-luc.michel@git.antfield.fr> References: <20170428125632.5704-1-luc.michel@git.antfield.fr> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 188.165.75.195 X-Mailman-Approved-At: Fri, 28 Apr 2017 09:41:34 -0400 Subject: [Qemu-devel] [PATCH 1/1] target/arm: add data cache invalidation cp15 instruction to cortex-r5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-trivial@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, Luc MICHEL Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The cp15, CRn=3D15, opc1=3D0, CRm=3D5, opc2=3D0 instruction invalidates all= the data cache on the cortex-r5. Implementing it as a NOP. Signed-off-by: Luc MICHEL --- target/arm/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b357aee778..47687a40c4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1062,6 +1062,8 @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_CONST }, { .name =3D "BTCM", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .= opc2 =3D 1, .access =3D PL1_RW, .type =3D ARM_CP_CONST }, + { .name =3D "DCACHE_INVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 15, .crm= =3D 5, + .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP }, REGINFO_SENTINEL }; =20 --=20 2.12.2