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[58.98.173.17]) by smtp.gmail.com with ESMTPSA id e24sm10672804pfd.17.2017.04.25.07.10.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 25 Apr 2017 07:10:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Dz96HGDayZk9jflzNvktzC9HUMFpTty/rGW3DI6gUls=; b=sTbvEpKbcnj9C9Oe8TNRYrfb7teRLkeQxZUScN21OJO9qV857MrK8Bj7NbFc5qajCX Za1qxH9lTpbljcNpHa6GCnGqa7RiKMp4kvA3Tdza66TrsRXXGBGpxEjRfl604miVHIzd StgQoDgrGDyRNup0NcQNvXQQRRbe725oGiF7J6bC+m1R+hojQIOxtytOursdHR1uAq1r bzGyOvxCWA0hkEEgB4lNTmcZrgl1hsr23cwe9+RGzTm4iey3IkqAwhUYsOOgPOAuPxNH 6gVuCyoiJU682VrYCAQcwdXGIipmWqw/vVdlDqaHb0Hcslc0hPEYSxgenMAcOKWz/hCK MwZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Dz96HGDayZk9jflzNvktzC9HUMFpTty/rGW3DI6gUls=; b=ZkHLEy0M92JwLSXMMhx5QhOCtz8nmnSeu77jsVM8v9CJ07kmUX0TBtRhtHtpYC1n2U ZDRXBBoajMfXG0+rS3+8wwCoS2F/CzgtnXFFr6iR878JW19ljlZaNwc7VN8Q0G1UmZnB EaTnjEb8uXBvxZGMkTdsMOH+q3z4mr4BM279BPkUOjdyeCcGrkys0fToh/qt9P23Mia/ YVpnmM913WfBvAuzkLDN5n51vQlfWa1hp0pgEbLDWaNXLLEUW9FtLVYpC8jw+K4E8+PW XWTiSXBstXAl1dZWVZRqGVKRg/b5n7B/kvjrXQCA+xWOFOty8gsryseSq20GhcKxemB5 nxhg== X-Gm-Message-State: AN3rC/6AJ4ENf3FXlOWlLAxwvBBrbDEE+xpd4dRHhd6CqqM+c01cnkBh rdkXbduJ79WdYQ== X-Received: by 10.99.55.75 with SMTP id g11mr28811431pgn.224.1493129459161; Tue, 25 Apr 2017 07:10:59 -0700 (PDT) From: Stafford Horne To: Richard Henderson Date: Tue, 25 Apr 2017 23:10:39 +0900 Message-Id: <20170425141039.11963-1-shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH RFC v2] target/openrisc: Support non-busy idle state using PMR SPR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , QEMU Development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The OpenRISC architecture has the Power Management Register (PMR) special purpose register to manage cpu power states. The interesting modes are: * Doze Mode (DME) - Stop cpu except timer & pic - wake on interrupt * Sleep Mode (SME) - Stop cpu and all units - wake on interrupt * Suspend Model (SUME) - Stop cpu and all units - wake on reset The linux kernel will set DME when idle. This patch implements the PMR SPR and halts the qemu cpu when there is a change to DME or SME. This means that openrisc qemu in no longer peggs a host cpu at 100%. In order for this to work we need to kick the CPU when timers are expired. Update the cpu timer to kick the cpu upon each timer event. Signed-off-by: Stafford Horne --- Hello, This patch seems work fine now. Changes since v1: * Changed to kick cpu in timer * Increment pc separate from restore hw/openrisc/cputimer.c | 1 + target/openrisc/cpu.c | 3 ++- target/openrisc/cpu.h | 10 ++++++++++ target/openrisc/interrupt.c | 2 ++ target/openrisc/machine.c | 1 + target/openrisc/sys_helper.c | 13 +++++++++++++ 6 files changed, 29 insertions(+), 1 deletion(-) diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c index a98c799..febc469 100644 --- a/hw/openrisc/cputimer.c +++ b/hw/openrisc/cputimer.c @@ -61,6 +61,7 @@ void cpu_openrisc_timer_update(OpenRISCCPU *cpu) } next =3D now + (uint64_t)wait * TIMER_PERIOD; timer_mod(cpu->env.timer, next); + qemu_cpu_kick(CPU(cpu)); } =20 void cpu_openrisc_count_start(OpenRISCCPU *cpu) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index c9b3f22..1d6330c 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -51,7 +51,8 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.lock_addr =3D -1; s->exception_index =3D -1; =20 - cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; + cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | + UPR_PMP; cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 <= < 2)); cpu->env.immucfgr =3D (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 <= < 2)); =20 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 938ccc3..2721432 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -140,6 +140,15 @@ enum { IMMUCFGR_HTR =3D (1 << 11), }; =20 +/* Power management register */ +enum { + PMR_SDF =3D (15 << 0), + PMR_DME =3D (1 << 4), + PMR_SME =3D (1 << 5), + PMR_DCGE =3D (1 << 6), + PMR_SUME =3D (1 << 7), +}; + /* Float point control status register */ enum { FPCSR_FPEE =3D 1, @@ -284,6 +293,7 @@ typedef struct CPUOpenRISCState { uint32_t immucfgr; /* IMMU configure register */ uint32_t esr; /* Exception supervisor register */ uint32_t evbar; /* Exception vector base address register */ + uint32_t pmr; /* Power Management Register */ uint32_t fpcsr; /* Float register */ float_status fp_status; =20 diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 2c91fab..3959671 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -60,6 +60,8 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->sr |=3D SR_SM; env->sr &=3D ~SR_IEE; env->sr &=3D ~SR_TEE; + env->pmr &=3D ~PMR_DME; + env->pmr &=3D ~PMR_SME; env->tlb->cpu_openrisc_map_address_data =3D &cpu_openrisc_get_phys_nom= mu; env->tlb->cpu_openrisc_map_address_code =3D &cpu_openrisc_get_phys_nom= mu; env->lock_addr =3D -1; diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index a82be62..a20cce7 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -138,6 +138,7 @@ static const VMStateDescription vmstate_env =3D { VMSTATE_UINT32(dmmucfgr, CPUOpenRISCState), VMSTATE_UINT32(immucfgr, CPUOpenRISCState), VMSTATE_UINT32(evbar, CPUOpenRISCState), + VMSTATE_UINT32(pmr, CPUOpenRISCState), VMSTATE_UINT32(esr, CPUOpenRISCState), VMSTATE_UINT32(fpcsr, CPUOpenRISCState), VMSTATE_UINT64(mac, CPUOpenRISCState), diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index fa3d6a4..44acf0d 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "exception.h" =20 #define TO_SPR(group, number) (((group) << 11) + (number)) =20 @@ -141,6 +142,15 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(5, 2): /* MACHI */ env->mac =3D deposit64(env->mac, 32, 32, rb); break; + case TO_SPR(8, 0): /* PMR */ + env->pmr =3D rb; + if (env->pmr & PMR_DME || env->pmr & PMR_SME) { + cpu_restore_state(cs, GETPC()); + env->pc +=3D 4; + cs->halted =3D 1; + raise_exception(cpu, EXCP_HLT); + } + break; case TO_SPR(9, 0): /* PICMR */ env->picmr |=3D rb; break; @@ -287,6 +297,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, return env->mac >> 32; break; =20 + case TO_SPR(8, 0): /* PMR */ + return env->pmr; + case TO_SPR(9, 0): /* PICMR */ return env->picmr; =20 --=20 2.9.3