From nobody Mon Feb 9 17:59:54 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493001372499814.874204228475; Sun, 23 Apr 2017 19:36:12 -0700 (PDT) Received: from localhost ([::1]:41503 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2TrG-0005XV-CU for importer@patchew.org; Sun, 23 Apr 2017 22:36:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56788) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2TIL-0001gz-Tk for qemu-devel@nongnu.org; Sun, 23 Apr 2017 22:00:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d2TIK-0003Zo-OZ for qemu-devel@nongnu.org; Sun, 23 Apr 2017 22:00:05 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:60329) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d2TIK-0003TR-1D; Sun, 23 Apr 2017 22:00:04 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 3wB8ff4gc7z9sN4; Mon, 24 Apr 2017 11:59:37 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1492999178; bh=HR0U39NnLgZbhVAgFna2gtjDBh4EeA62nYA0GLxJ5gc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OTWH9bVumAHUSw+KvOSu4EUJy8RjZ+2lBf/d4H3cpv/asFykd/oI/7UVZBSymMHRG OtxFmazThLtAbv6NGG4lt6Cmx0+VCqhnjsvu/7Lcs602qEMFeJE+poY0gVl/p6mYQB ZpDa4cRbBnrR70w7EPTxvKG3ugtoK7f2H69SOv7I= From: David Gibson To: peter.maydell@linaro.org Date: Mon, 24 Apr 2017 11:59:17 +1000 Message-Id: <20170424015927.8933-38-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170424015927.8933-1-david@gibson.dropbear.id.au> References: <20170424015927.8933-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 37/47] ppc/pnv: enable only one LPC bus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mdroth@linux.vnet.ibm.com, aik@ozlabs.ru, qemu-devel@nongnu.org, agraf@suse.de, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: C=C3=A9dric Le Goater The default LPC bus of a multichip system is on chip 0. It's recognized by the firmware (skiboot) using a "primary" property in the device tree. We introduce a pnv_chip_lpc_offset() routine to locate the LPC node of a chip and set the property directly from the machine level. Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv.c | 22 ++++++++++++++++++++++ hw/ppc/pnv_lpc.c | 9 --------- 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 27589b9..9468e99 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -255,6 +255,18 @@ static void powernv_populate_icp(PnvChip *chip, void *= fdt, uint32_t pir, g_free(reg); } =20 +static int pnv_chip_lpc_offset(PnvChip *chip, void *fdt) +{ + char *name; + int offset; + + name =3D g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", + (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_= BASE); + offset =3D fdt_path_offset(fdt, name); + g_free(name); + return offset; +} + static void powernv_populate_chip(PnvChip *chip, void *fdt) { PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); @@ -264,6 +276,16 @@ static void powernv_populate_chip(PnvChip *chip, void = *fdt) =20 pnv_xscom_populate(chip, fdt, 0); =20 + /* The default LPC bus of a multichip system is on chip 0. It's + * recognized by the firmware (skiboot) using a "primary" + * property. + */ + if (chip->chip_id =3D=3D 0x0) { + int lpc_offset =3D pnv_chip_lpc_offset(chip, fdt); + + _FDT((fdt_setprop(fdt, lpc_offset, "primary", NULL, 0))); + } + for (i =3D 0; i < chip->nr_cores; i++) { PnvCore *pnv_core =3D PNV_CORE(chip->cores + i * typesize); =20 diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 5d20c15..f03a80a 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -92,14 +92,6 @@ enum { #define LPC_HC_REGS_OPB_SIZE 0x00001000 =20 =20 -/* - * TODO: the "primary" cell should only be added on chip 0. This is - * how skiboot chooses the default LPC controller on multichip - * systems. - * - * It would be easly done if we can change the populate() interface to - * replace the PnvXScomInterface parameter by a PnvChip one - */ static int pnv_lpc_populate(PnvXScomInterface *dev, void *fdt, int xscom_o= ffset) { const char compat[] =3D "ibm,power8-lpc\0ibm,lpc"; @@ -119,7 +111,6 @@ static int pnv_lpc_populate(PnvXScomInterface *dev, voi= d *fdt, int xscom_offset) _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2))); _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1))); - _FDT((fdt_setprop(fdt, offset, "primary", NULL, 0))); _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); return 0; } --=20 2.9.3