From nobody Mon Feb 9 19:54:25 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149300118075911.296563638891257; Sun, 23 Apr 2017 19:33:00 -0700 (PDT) Received: from localhost ([::1]:41475 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2ToB-00031w-7Q for importer@patchew.org; Sun, 23 Apr 2017 22:32:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56830) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2TIM-0001h6-NB for qemu-devel@nongnu.org; Sun, 23 Apr 2017 22:00:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d2TIK-0003a5-Vl for qemu-devel@nongnu.org; Sun, 23 Apr 2017 22:00:06 -0400 Received: from ozlabs.org ([103.22.144.67]:54591) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d2TIJ-0003WU-Os; Sun, 23 Apr 2017 22:00:04 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 3wB8fg17Z0z9sD5; Mon, 24 Apr 2017 11:59:37 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1492999179; bh=7gFf/VAX45UWsMoEH/wP42BGFpzA7oE1twq6gceoGhI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VLgD9rQUU4XcQ6JP2TXrel4rmZ8CXpD6HjhC5+bQA/Nh62rqGgQWrxha+CXB3gmVV l+fTT3yJPOqg3/quFMgm7xTkbFxYEjwrmEpmMx67KAlNHydVVG06ggom3jC+UiBkP0 SaA+LN2WjXYDRWVKFFTTE+GuGsgm2fJ1aLWAfAtI= From: David Gibson To: peter.maydell@linaro.org Date: Mon, 24 Apr 2017 11:59:16 +1000 Message-Id: <20170424015927.8933-37-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170424015927.8933-1-david@gibson.dropbear.id.au> References: <20170424015927.8933-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 36/47] ppc/pnv: Add support for POWER8+ LPC Controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mdroth@linux.vnet.ibm.com, aik@ozlabs.ru, qemu-devel@nongnu.org, agraf@suse.de, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Benjamin Herrenschmidt It adds the Naples chip which supports proper LPC interrupts via the LPC controller rather than via an external CPLD. Signed-off-by: Benjamin Herrenschmidt [clg: - updated for qemu-2.9 - ported on latest PowerNV patchset - moved the IRQ handler in pnv_lpc.c - introduced pnv_lpc_isa_irq_create() to create the ISA IRQs ] Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv.c | 45 +++------------------- hw/ppc/pnv_lpc.c | 97 ++++++++++++++++++++++++++++++++++++++++++++= +++- include/hw/ppc/pnv_lpc.h | 8 ++++ 3 files changed, 108 insertions(+), 42 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 16f32c9..27589b9 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -346,36 +346,6 @@ static void ppc_powernv_reset(void) cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); } =20 -/* If we don't use the built-in LPC interrupt deserializer, we need - * to provide a set of qirqs for the ISA bus or things will go bad. - * - * Most machines using pre-Naples chips (without said deserializer) - * have a CPLD that will collect the SerIRQ and shoot them as a - * single level interrupt to the P8 chip. So let's setup a hook - * for doing just that. - */ -static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level) -{ - PnvMachineState *pnv =3D POWERNV_MACHINE(qdev_get_machine()); - uint32_t old_state =3D pnv->cpld_irqstate; - PnvChip *chip =3D opaque; - - if (level) { - pnv->cpld_irqstate |=3D 1u << n; - } else { - pnv->cpld_irqstate &=3D ~(1u << n); - } - if (pnv->cpld_irqstate !=3D old_state) { - pnv_psi_irq_set(&chip->psi, PSIHB_IRQ_EXTERNAL, - pnv->cpld_irqstate !=3D 0); - } -} - -static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level) -{ - /* XXX TODO */ -} - static ISABus *pnv_isa_create(PnvChip *chip) { PnvLpcController *lpc =3D &chip->lpc; @@ -390,16 +360,7 @@ static ISABus *pnv_isa_create(PnvChip *chip) isa_bus =3D isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, &error_fatal); =20 - /* Not all variants have a working serial irq decoder. If not, - * handling of LPC interrupts becomes a platform issue (some - * platforms have a CPLD to do it). - */ - if (pcc->chip_type =3D=3D PNV_CHIP_POWER8NVL) { - irqs =3D qemu_allocate_irqs(pnv_lpc_isa_irq_handler, chip, ISA_NUM= _IRQS); - } else { - irqs =3D qemu_allocate_irqs(pnv_lpc_isa_irq_handler_cpld, chip, - ISA_NUM_IRQS); - } + irqs =3D pnv_lpc_isa_irq_create(lpc, pcc->chip_type, ISA_NUM_IRQS); =20 isa_bus_irqs(isa_bus, irqs); return isa_bus; @@ -699,6 +660,10 @@ static void pnv_chip_init(Object *obj) object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL); object_property_add_const_link(OBJECT(&chip->occ), "psi", OBJECT(&chip->psi), &error_abort); + + /* The LPC controller needs PSI to generate interrupts */ + object_property_add_const_link(OBJECT(&chip->lpc), "psi", + OBJECT(&chip->psi), &error_abort); } =20 static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 78db524..5d20c15 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -250,6 +250,34 @@ static const MemoryRegionOps pnv_lpc_xscom_ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 +static void pnv_lpc_eval_irqs(PnvLpcController *lpc) +{ + bool lpc_to_opb_irq =3D false; + + /* Update LPC controller to OPB line */ + if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) { + uint32_t irqs; + + irqs =3D lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask; + lpc_to_opb_irq =3D (irqs !=3D 0); + } + + /* We don't honor the polarity register, it's pointless and unused + * anyway + */ + if (lpc_to_opb_irq) { + lpc->opb_irq_input |=3D OPB_MASTER_IRQ_LPC; + } else { + lpc->opb_irq_input &=3D ~OPB_MASTER_IRQ_LPC; + } + + /* Update OPB internal latch */ + lpc->opb_irq_stat |=3D lpc->opb_irq_input & lpc->opb_irq_mask; + + /* Reflect the interrupt */ + pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_LPC_I2C, lpc->opb_irq_stat !=3D 0); +} + static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size) { PnvLpcController *lpc =3D opaque; @@ -300,12 +328,15 @@ static void lpc_hc_write(void *opaque, hwaddr addr, u= int64_t val, break; case LPC_HC_IRQSER_CTRL: lpc->lpc_hc_irqser_ctrl =3D val; + pnv_lpc_eval_irqs(lpc); break; case LPC_HC_IRQMASK: lpc->lpc_hc_irqmask =3D val; + pnv_lpc_eval_irqs(lpc); break; case LPC_HC_IRQSTAT: lpc->lpc_hc_irqstat &=3D ~val; + pnv_lpc_eval_irqs(lpc); break; case LPC_HC_ERROR_ADDRESS: break; @@ -363,14 +394,15 @@ static void opb_master_write(void *opaque, hwaddr add= r, switch (addr) { case OPB_MASTER_LS_IRQ_STAT: lpc->opb_irq_stat &=3D ~val; + pnv_lpc_eval_irqs(lpc); break; case OPB_MASTER_LS_IRQ_MASK: - /* XXX Filter out reserved bits */ lpc->opb_irq_mask =3D val; + pnv_lpc_eval_irqs(lpc); break; case OPB_MASTER_LS_IRQ_POL: - /* XXX Filter out reserved bits */ lpc->opb_irq_pol =3D val; + pnv_lpc_eval_irqs(lpc); break; case OPB_MASTER_LS_IRQ_INPUT: /* Read only */ @@ -398,6 +430,8 @@ static const MemoryRegionOps opb_master_ops =3D { static void pnv_lpc_realize(DeviceState *dev, Error **errp) { PnvLpcController *lpc =3D PNV_LPC(dev); + Object *obj; + Error *error =3D NULL; =20 /* Reg inits */ lpc->lpc_hc_fw_rd_acc_size =3D LPC_HC_FW_RD_4B; @@ -441,6 +475,15 @@ static void pnv_lpc_realize(DeviceState *dev, Error **= errp) pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(dev), &pnv_lpc_xscom_ops, lpc, "xscom-lpc", PNV_XSCOM_LPC_SIZE); + + /* get PSI object from chip */ + obj =3D object_property_get_link(OBJECT(dev), "psi", &error); + if (!obj) { + error_setg(errp, "%s: required link 'psi' not found: %s", + __func__, error_get_pretty(error)); + return; + } + lpc->psi =3D PNV_PSI(obj); } =20 static void pnv_lpc_class_init(ObjectClass *klass, void *data) @@ -470,3 +513,53 @@ static void pnv_lpc_register_types(void) } =20 type_init(pnv_lpc_register_types) + +/* If we don't use the built-in LPC interrupt deserializer, we need + * to provide a set of qirqs for the ISA bus or things will go bad. + * + * Most machines using pre-Naples chips (without said deserializer) + * have a CPLD that will collect the SerIRQ and shoot them as a + * single level interrupt to the P8 chip. So let's setup a hook + * for doing just that. + */ +static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level) +{ + PnvMachineState *pnv =3D POWERNV_MACHINE(qdev_get_machine()); + uint32_t old_state =3D pnv->cpld_irqstate; + PnvLpcController *lpc =3D PNV_LPC(opaque); + + if (level) { + pnv->cpld_irqstate |=3D 1u << n; + } else { + pnv->cpld_irqstate &=3D ~(1u << n); + } + + if (pnv->cpld_irqstate !=3D old_state) { + pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_EXTERNAL, pnv->cpld_irqstate != =3D 0); + } +} + +static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level) +{ + PnvLpcController *lpc =3D PNV_LPC(opaque); + + /* The Naples HW latches the 1 levels, clearing is done by SW */ + if (level) { + lpc->lpc_hc_irqstat |=3D LPC_HC_IRQ_SERIRQ0 >> n; + pnv_lpc_eval_irqs(lpc); + } +} + +qemu_irq *pnv_lpc_isa_irq_create(PnvLpcController *lpc, int chip_type, + int nirqs) +{ + /* Not all variants have a working serial irq decoder. If not, + * handling of LPC interrupts becomes a platform issue (some + * platforms have a CPLD to do it). + */ + if (chip_type =3D=3D PNV_CHIP_POWER8NVL) { + return qemu_allocate_irqs(pnv_lpc_isa_irq_handler, lpc, nirqs); + } else { + return qemu_allocate_irqs(pnv_lpc_isa_irq_handler_cpld, lpc, nirqs= ); + } +} diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index 38e5506..ccf969a 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -23,6 +23,8 @@ #define PNV_LPC(obj) \ OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV_LPC) =20 +typedef struct PnvPsi PnvPsi; + typedef struct PnvLpcController { DeviceState parent; =20 @@ -62,6 +64,12 @@ typedef struct PnvLpcController { =20 /* XSCOM registers */ MemoryRegion xscom_regs; + + /* PSI to generate interrupts */ + PnvPsi *psi; } PnvLpcController; =20 +qemu_irq *pnv_lpc_isa_irq_create(PnvLpcController *lpc, int chip_type, + int nirqs); + #endif /* _PPC_PNV_LPC_H */ --=20 2.9.3