From nobody Wed May 1 22:27:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1492984549347352.58001412526346; Sun, 23 Apr 2017 14:55:49 -0700 (PDT) Received: from localhost ([::1]:40727 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2PTv-0002cu-NO for importer@patchew.org; Sun, 23 Apr 2017 17:55:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47625) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2PTA-0002Eu-Nm for qemu-devel@nongnu.org; Sun, 23 Apr 2017 17:55:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d2PT5-0004Ul-Rw for qemu-devel@nongnu.org; Sun, 23 Apr 2017 17:55:00 -0400 Received: from mail-it0-x243.google.com ([2607:f8b0:4001:c0b::243]:36770) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d2PT5-0004Uh-MN for qemu-devel@nongnu.org; Sun, 23 Apr 2017 17:54:55 -0400 Received: by mail-it0-x243.google.com with SMTP id x188so10999412itb.3 for ; Sun, 23 Apr 2017 14:54:55 -0700 (PDT) Received: from localhost (z64.124-44-184.ppp.wakwak.ne.jp. [124.44.184.64]) by smtp.gmail.com with ESMTPSA id j30sm1833437pgn.47.2017.04.23.14.54.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 23 Apr 2017 14:54:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BpkoPozLSCBNy1GrHNzK20dsKh7vFoYjPz13ivM248M=; b=AZgH7fcKMgmOEsE4EWfxOlGi8b5GTkDvPDC7ug3aSp8lLxwrRMyd0o8DNwnxO0KKod NcvyL4E5ja357A++MgCcdxi2qieiJDpReleiyCWqCRyx+0C6rPOFOHQQYpn6lLCmA/gH xSCzk8J17ttbUkPxDucTN2qVxQqTClDA3YUwWoFZktO1VFcmDHaoTO7eWt+j8pntNkEN c4VAxaH7a/0iMjhOLUlnjHvEvLq1EfctP+rw+tMc0DJ4oysDM405uK0KWDwTeu1YLhkp i+SpbiI2R6obvtNzrMPV7dn+oGcFu2cIfBiOGJNz+Ztva8PMrD+7fPISgWxamsah3WPQ rFsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BpkoPozLSCBNy1GrHNzK20dsKh7vFoYjPz13ivM248M=; b=m9yz5oDGzEf+/uXQ86WV6gdyDv9Msulm7nfVyHT5l0+pZauy2uC5Efh5SNKRzmQJzS 2b4SAZBx20pTX7AGtew5qCFMGSHefiZVCDfrvEA+oFl8pih9U0OD7UclhU7qGZ9PO2Ve 2q/1wdoWLMTgrUiMKHxCDaUrSSW6GiR2FwdZ05VMCCFFYNRQJTQGb464FcXr6ywU0mpv pTfKDXig1RMHbM7yodh6504vwK7fdavdOhk7YVaENQdAX943OvEmiFyRmwyomXXZ74Iv I09vBgRsc+ck/BLhlWA/DNWqa2cGvEMxDI3CKkRhhfOPAIyMISEYxooJXMLKF2PHPlng lTPA== X-Gm-Message-State: AN3rC/7eqfR0Iw/AbHe0jFZN0HS+oeoWxVZgLG4iEu2kcrfIJebyuLTo UsIRDz5fXaIHfQ== X-Received: by 10.99.54.70 with SMTP id d67mr13600088pga.24.1492984494596; Sun, 23 Apr 2017 14:54:54 -0700 (PDT) From: Stafford Horne To: Richard Henderson Date: Mon, 24 Apr 2017 06:54:20 +0900 Message-Id: <20170423215420.27098-1-shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::243 Subject: [Qemu-devel] [PATCH RFC] target/openrisc: Support non-busy idle state using PMR SPR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , QEMU Development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The OpenRISC architecture has the Power Management Register (PMR) special purpose register to manage cpu power states. The interesting modes are: * Doze Mode (DME) - Stop cpu except timer & pic - wake on interrupt * Sleep Mode (SME) - Stop cpu and all units - wake on interrupt * Suspend Model (SUME) - Stop cpu and all units - wake on reset The linux kernel will set DME when idle. This patch implements the PMR SPR and halts the qemu cpu when there is a change to DME or SME. This means that openrisc qemu in no longer peggs a host cpu at 100%. Signed-off-by: Stafford Horne --- (Sorry, resending this again, there was something wrong with my mail setup on the last) Hello, This patch seems work fine but I am not sure if it is the right way to do trigger the halt signal. Should I do it via raising an interrupt or exception and exitting the cpu? Also, I don't know if its due to this patch of an issue with the timer interrupts. After applying this patch the timer interrupts do not trigger until a keypress is make. i.e. something like this... $ sleep 5 It may or may not be related to this patch as I noticed sometime things like this happened before this patch. target/openrisc/cpu.c | 3 ++- target/openrisc/cpu.h | 10 ++++++++++ target/openrisc/interrupt.c | 2 ++ target/openrisc/machine.c | 1 + target/openrisc/sys_helper.c | 12 ++++++++++++ 5 files changed, 27 insertions(+), 1 deletion(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index c9b3f22..1d6330c 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -51,7 +51,8 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.lock_addr =3D -1; s->exception_index =3D -1; =20 - cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; + cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | + UPR_PMP; cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 <= < 2)); cpu->env.immucfgr =3D (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 <= < 2)); =20 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 938ccc3..2721432 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -140,6 +140,15 @@ enum { IMMUCFGR_HTR =3D (1 << 11), }; =20 +/* Power management register */ +enum { + PMR_SDF =3D (15 << 0), + PMR_DME =3D (1 << 4), + PMR_SME =3D (1 << 5), + PMR_DCGE =3D (1 << 6), + PMR_SUME =3D (1 << 7), +}; + /* Float point control status register */ enum { FPCSR_FPEE =3D 1, @@ -284,6 +293,7 @@ typedef struct CPUOpenRISCState { uint32_t immucfgr; /* IMMU configure register */ uint32_t esr; /* Exception supervisor register */ uint32_t evbar; /* Exception vector base address register */ + uint32_t pmr; /* Power Management Register */ uint32_t fpcsr; /* Float register */ float_status fp_status; =20 diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 2c91fab..3959671 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -60,6 +60,8 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->sr |=3D SR_SM; env->sr &=3D ~SR_IEE; env->sr &=3D ~SR_TEE; + env->pmr &=3D ~PMR_DME; + env->pmr &=3D ~PMR_SME; env->tlb->cpu_openrisc_map_address_data =3D &cpu_openrisc_get_phys_nom= mu; env->tlb->cpu_openrisc_map_address_code =3D &cpu_openrisc_get_phys_nom= mu; env->lock_addr =3D -1; diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index a82be62..a20cce7 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -138,6 +138,7 @@ static const VMStateDescription vmstate_env =3D { VMSTATE_UINT32(dmmucfgr, CPUOpenRISCState), VMSTATE_UINT32(immucfgr, CPUOpenRISCState), VMSTATE_UINT32(evbar, CPUOpenRISCState), + VMSTATE_UINT32(pmr, CPUOpenRISCState), VMSTATE_UINT32(esr, CPUOpenRISCState), VMSTATE_UINT32(fpcsr, CPUOpenRISCState), VMSTATE_UINT64(mac, CPUOpenRISCState), diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index fa3d6a4..cb1e085 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "exception.h" =20 #define TO_SPR(group, number) (((group) << 11) + (number)) =20 @@ -141,6 +142,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(5, 2): /* MACHI */ env->mac =3D deposit64(env->mac, 32, 32, rb); break; + case TO_SPR(8, 0): /* PMR */ + env->pmr =3D rb; + if (env->pmr & PMR_DME || env->pmr & PMR_SME) { + cpu_restore_state(cs, GETPC() + 4); + cs->halted =3D 1; + raise_exception(cpu, EXCP_HLT); + } + break; case TO_SPR(9, 0): /* PICMR */ env->picmr |=3D rb; break; @@ -287,6 +296,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, return env->mac >> 32; break; =20 + case TO_SPR(8, 0): /* PMR */ + return env->pmr; + case TO_SPR(9, 0): /* PICMR */ return env->picmr; =20 --=20 2.9.3