From nobody Mon Feb 9 16:01:41 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1492496398786657.5944756885206; Mon, 17 Apr 2017 23:19:58 -0700 (PDT) Received: from localhost ([::1]:40245 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0MUW-0005P3-Kz for importer@patchew.org; Tue, 18 Apr 2017 02:19:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56737) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0MSd-0004Pd-NY for qemu-devel@nongnu.org; Tue, 18 Apr 2017 02:18:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d0MSa-0004w8-Hy for qemu-devel@nongnu.org; Tue, 18 Apr 2017 02:17:59 -0400 Received: from mail-pf0-x22a.google.com ([2607:f8b0:400e:c00::22a]:34239) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d0MSa-0004w0-C2 for qemu-devel@nongnu.org; Tue, 18 Apr 2017 02:17:56 -0400 Received: by mail-pf0-x22a.google.com with SMTP id c198so76057926pfc.1 for ; Mon, 17 Apr 2017 23:17:56 -0700 (PDT) Received: from tansell-z840-l.syd.corp.google.com ([100.64.125.243]) by smtp.gmail.com with ESMTPSA id e131sm15538458pfg.10.2017.04.17.23.17.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Apr 2017 23:17:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mithis.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UtDn17RrcAV5iBZ4y2PAsx8choiULHG/iv3YsNIcmoI=; b=lj5gRJacRnk92zgL1tGX7bsJ0pno4ICo4+/7W6bDl4t5/3jS/XNcNcKKguK0c+L9uY KV5WL3zkhlUpSWzjbFlOj6xOB87K5ujAj3IP1//xZ2HihSidzJ6IenGH0iE6X+3vJmRP 6PQxtdTr6bZfKerJmgQxJ9JP759fxhThnAD8g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UtDn17RrcAV5iBZ4y2PAsx8choiULHG/iv3YsNIcmoI=; b=GSEqpHkOc6gOTBGJZ4kGbaoY8rViCn45wt0MEclo2b6taIzUK031t/9YwyzaWVdZeg e8vacqZi47LWvONoWJFUitM2dLOwW7gtXYLjpzBLpfe/m0mgQqCeDO0i8BQvjwRdT99o rdZl6UmWWgJ8afhaR7IC6bDOBrTEyoCJ1V5ugTArPrKVIRd+xm6cQtQlJO9SyTfXNxPU 9uZFwOhlYt4WSR4n+pWSxP9MVayYwJjgtfLWso6SSqe37ncij/pPWLg4Agm1rIhDu8Ec kdWgw7lgR4xnSQ8Rvwz3VWBVz/OBd8s3IDjB0NMLufAkjedPBte2Beg6JJiy8qyWa3Tl I2ZQ== X-Gm-Message-State: AN3rC/73ThVdWNVJ1K2I4kRoYgHWQAN9/i1VK+IiZohIjiZ34D+JIfv5 8QSKVJglWeyccrbV8MyTRA== X-Received: by 10.98.155.206 with SMTP id e75mr16441489pfk.24.1492496275336; Mon, 17 Apr 2017 23:17:55 -0700 (PDT) From: Tim 'mithro' Ansell To: qemu-devel@nongnu.org Date: Tue, 18 Apr 2017 16:15:51 +1000 Message-Id: <20170418061551.196582-3-mithro@mithis.com> X-Mailer: git-send-email 2.12.2.762.g0e3151a226-goog In-Reply-To: <20170418061551.196582-1-mithro@mithis.com> References: <20170418061551.196582-1-mithro@mithis.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22a Subject: [Qemu-devel] [PATCH 2/2] target/openrisc: Implement EPH bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com, Jia Liu , Tim 'mithro' Ansell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Exception Prefix High (EPH) control bit of the Supervision Register (SR). The significant bits (31-12) of the vector offset address for each exception depend on the setting of the Supervision Register (SR)'s EPH bit and the Exception Vector Base Address Register (EVBAR). If SR[EPH] is set, the vector offset is logically ORed with the offset 0xF0000000. This means if EPH is; * 0 - Exceptions vectors start at EVBAR * 1 - Exception vectors start at EVBAR | 0xF0000000 Signed-off-by: Tim 'mithro' Ansell Acked-by: Stafford Horne --- target/openrisc/interrupt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 78f0ba9421..2c91fab380 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -69,6 +69,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs) if (env->cpucfgr & CPUCFGR_EVBARP) { vect_pc |=3D env->evbar; } + if (env->sr & SR_EPH) { + vect_pc |=3D 0xf0000000; + } env->pc =3D vect_pc; } else { cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); --=20 2.12.1