From nobody Tue Feb 10 13:01:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1490949817360893.7983250109545; Fri, 31 Mar 2017 01:43:37 -0700 (PDT) Received: from localhost ([::1]:39560 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cts9f-0000aB-P9 for importer@patchew.org; Fri, 31 Mar 2017 04:43:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54909) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cts8d-0008QQ-Cb for qemu-devel@nongnu.org; Fri, 31 Mar 2017 04:42:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cts8Z-000235-CJ for qemu-devel@nongnu.org; Fri, 31 Mar 2017 04:42:31 -0400 Received: from mga03.intel.com ([134.134.136.65]:21496) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cts8Z-00020h-3V for qemu-devel@nongnu.org; Fri, 31 Mar 2017 04:42:27 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Mar 2017 01:42:26 -0700 Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.159.153]) by fmsmga002.fm.intel.com with ESMTP; 31 Mar 2017 01:42:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490949747; x=1522485747; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=YqurXLSNySf0wBz3JceEkU7P+gU9FzMZ9v2DpCUVgRw=; b=wcuZLTxnQix4Kukph6+t90cBj8hUL8l3I9Zm0UKWl1r8yh+pWsXZhmFG asfhIzBEMLLAsJH5SWY6ljrYXit9Jg==; X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,251,1486454400"; d="scan'208";a="1149181040" From: Haozhong Zhang To: qemu-devel@nongnu.org Date: Fri, 31 Mar 2017 16:41:45 +0800 Message-Id: <20170331084147.32716-3-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170331084147.32716-1-haozhong.zhang@intel.com> References: <20170331084147.32716-1-haozhong.zhang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.65 Subject: [Qemu-devel] [RFC PATCH 2/4] nvdimm: add functions to initialize and perform flush on back store X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haozhong Zhang , dan.j.williams@intel.com, Xiao Guangrong , Igor Mammedov , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" fsync() is used to persist modifications to the back store. If the host NVDIMM is used as the back store, fsync() on Linux will trigger the write to the host flush hint address. Signed-off-by: Haozhong Zhang --- hw/mem/nvdimm.c | 22 ++++++++++++++++++++++ include/hw/mem/nvdimm.h | 13 +++++++++++++ 2 files changed, 35 insertions(+) diff --git a/hw/mem/nvdimm.c b/hw/mem/nvdimm.c index db896b0..484ab8b 100644 --- a/hw/mem/nvdimm.c +++ b/hw/mem/nvdimm.c @@ -78,6 +78,26 @@ static MemoryRegion *nvdimm_get_memory_region(PCDIMMDevi= ce *dimm) return &nvdimm->nvdimm_mr; } =20 +static void nvdimm_flush_init(NVDIMMDevice *nvdimm, MemoryRegion *hostmem_= mr) +{ + if (nvdimm->flush_hint_enabled) { + nvdimm->backend_fd =3D memory_region_get_fd(hostmem_mr); + } else { + nvdimm->backend_fd =3D -1; + } +} + +void nvdimm_flush(NVDIMMDevice *nvdimm) +{ + if (nvdimm->backend_fd !=3D -1) { + /* + * If the backend store is a physical NVDIMM device, fsync() + * will trigger the flush via the flush hint on the host device. + */ + fsync(nvdimm->backend_fd); + } +} + static void nvdimm_realize(PCDIMMDevice *dimm, Error **errp) { MemoryRegion *mr =3D host_memory_backend_get_memory(dimm->hostmem, err= p); @@ -105,6 +125,8 @@ static void nvdimm_realize(PCDIMMDevice *dimm, Error **= errp) memory_region_init_alias(&nvdimm->nvdimm_mr, OBJECT(dimm), "nvdimm-memory", mr, 0, pmem_size); nvdimm->nvdimm_mr.align =3D align; + + nvdimm_flush_init(nvdimm, mr); } =20 /* diff --git a/include/hw/mem/nvdimm.h b/include/hw/mem/nvdimm.h index 03e1ff9..eb71f41 100644 --- a/include/hw/mem/nvdimm.h +++ b/include/hw/mem/nvdimm.h @@ -71,6 +71,18 @@ struct NVDIMMDevice { * guest via ACPI NFIT and _FIT method if NVDIMM hotplug is supported. */ MemoryRegion nvdimm_mr; + + /* + * If true, a flush hint address structure will be built for this + * NVDIMM device. + */ + bool flush_hint_enabled; + /* + * File descriptor of the backend store, which is used in nvdimm + * flush. It's cached in NVDIMMDevice rather than being fetched + * at each request in order to accelerate the flush a little bit. + */ + int backend_fd; }; typedef struct NVDIMMDevice NVDIMMDevice; =20 @@ -132,4 +144,5 @@ void nvdimm_build_acpi(GArray *table_offsets, GArray *t= able_data, uint32_t ram_slots); void nvdimm_plug(AcpiNVDIMMState *state); void nvdimm_acpi_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev); +void nvdimm_flush(NVDIMMDevice *nvdimm); #endif --=20 2.10.1