From nobody Sun Apr 28 00:40:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1490949921217658.2534941896218; Fri, 31 Mar 2017 01:45:21 -0700 (PDT) Received: from localhost ([::1]:39571 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ctsBL-0001sl-Nx for importer@patchew.org; Fri, 31 Mar 2017 04:45:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54907) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cts8d-0008QP-CI for qemu-devel@nongnu.org; Fri, 31 Mar 2017 04:42:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cts8Y-00021s-F1 for qemu-devel@nongnu.org; Fri, 31 Mar 2017 04:42:31 -0400 Received: from mga03.intel.com ([134.134.136.65]:21496) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cts8Y-00020h-3W for qemu-devel@nongnu.org; Fri, 31 Mar 2017 04:42:26 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Mar 2017 01:42:24 -0700 Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.159.153]) by fmsmga002.fm.intel.com with ESMTP; 31 Mar 2017 01:42:23 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490949746; x=1522485746; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=SSYFuwEkOCg6guDbAj0I2ZZ2HFvqwDMebB9eCAYCao8=; b=PyiwaL0J6dU0btRC1YPNWK1foyv+f3EPGWqznXrFOwNKY4KDYILr9hpd pGycxkKX4V/oeRJqX+SHOMpcHV58Fg==; X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,251,1486454400"; d="scan'208";a="1149181031" From: Haozhong Zhang To: qemu-devel@nongnu.org Date: Fri, 31 Mar 2017 16:41:44 +0800 Message-Id: <20170331084147.32716-2-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170331084147.32716-1-haozhong.zhang@intel.com> References: <20170331084147.32716-1-haozhong.zhang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.65 Subject: [Qemu-devel] [RFC PATCH 1/4] pc-dimm: add 'reserved-size' to reserve address range after the ending address X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haozhong Zhang , dan.j.williams@intel.com, Xiao Guangrong , Igor Mammedov , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" If option 'reserved-size=3DRSVD' is present, QEMU will reserve an address range of size 'RSVD' after the ending address of pc-dimm device. For the following example, -object memory-backend-file,id=3Dmem0,size=3D4G,... -device nvdimm,id=3Ddimm0,memdev=3Dmem0,reserved-size=3D4K,... -device pc-dimm,id=3Ddimm1,... if dimm0 is allocated to address N ~ N+4G, the address range of dimm1 will start from N+4G+4K or higher. Its current usage is to reserve spaces for flush hint addresses of nvdimm devices. Signed-off-by: Haozhong Zhang --- hw/mem/pc-dimm.c | 48 ++++++++++++++++++++++++++++++++++++++++++++= +--- include/hw/mem/pc-dimm.h | 2 ++ 2 files changed, 47 insertions(+), 3 deletions(-) diff --git a/hw/mem/pc-dimm.c b/hw/mem/pc-dimm.c index 9e8dab0..13dcd71 100644 --- a/hw/mem/pc-dimm.c +++ b/hw/mem/pc-dimm.c @@ -28,6 +28,7 @@ #include "sysemu/kvm.h" #include "trace.h" #include "hw/virtio/vhost.h" +#include "exec/address-spaces.h" =20 typedef struct pc_dimms_capacity { uint64_t size; @@ -44,7 +45,12 @@ void pc_dimm_memory_plug(DeviceState *dev, MemoryHotplug= State *hpms, MemoryRegion *vmstate_mr =3D ddc->get_vmstate_memory_region(dimm); Error *local_err =3D NULL; uint64_t existing_dimms_capacity =3D 0; - uint64_t addr; + uint64_t addr, size =3D memory_region_size(mr); + + size +=3D object_property_get_int(OBJECT(dimm), PC_DIMM_RSVD_PROP, &lo= cal_err); + if (local_err) { + goto out; + } =20 addr =3D object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &loc= al_err); if (local_err) { @@ -54,7 +60,7 @@ void pc_dimm_memory_plug(DeviceState *dev, MemoryHotplugS= tate *hpms, addr =3D pc_dimm_get_free_addr(hpms->base, memory_region_size(&hpms->mr), !addr ? NULL : &addr, align, - memory_region_size(mr), &local_err); + size, &local_err); if (local_err) { goto out; } @@ -64,7 +70,7 @@ void pc_dimm_memory_plug(DeviceState *dev, MemoryHotplugS= tate *hpms, goto out; } =20 - if (existing_dimms_capacity + memory_region_size(mr) > + if (existing_dimms_capacity + size > machine->maxram_size - machine->ram_size) { error_setg(&local_err, "not enough space, currently 0x%" PRIx64 " in use of total hot pluggable 0x" RAM_ADDR_FMT, @@ -315,6 +321,9 @@ uint64_t pc_dimm_get_free_addr(uint64_t address_space_s= tart, PCDIMMDevice *dimm =3D item->data; uint64_t dimm_size =3D object_property_get_int(OBJECT(dimm), PC_DIMM_SIZE_PROP, + errp) + + object_property_get_int(OBJECT(dimm), + PC_DIMM_RSVD_PROP, errp); if (errp && *errp) { goto out; @@ -382,6 +391,37 @@ static void pc_dimm_check_memdev_is_busy(Object *obj, = const char *name, error_propagate(errp, local_err); } =20 +static void pc_dimm_get_reserved_size(Object *obj, Visitor *v, const char = *name, + void *opaque, Error **errp) +{ + PCDIMMDevice *dimm =3D PC_DIMM(obj); + uint64_t value =3D dimm->reserved_size; + + visit_type_size(v, name, &value, errp); +} + +static void pc_dimm_set_reserved_size(Object *obj, Visitor *v, const char = *name, + void *opaque, Error **errp) +{ + PCDIMMDevice *dimm =3D PC_DIMM(obj); + Error *local_err =3D NULL; + uint64_t value; + + if (dimm->reserved_size) { + error_setg(&local_err, "cannot change 'reserved-size'"); + goto out; + } + + visit_type_size(v, name, &value, &local_err); + if (local_err) { + goto out; + } + dimm->reserved_size =3D value; + + out: + error_propagate(errp, local_err); +} + static void pc_dimm_init(Object *obj) { PCDIMMDevice *dimm =3D PC_DIMM(obj); @@ -393,6 +433,8 @@ static void pc_dimm_init(Object *obj) pc_dimm_check_memdev_is_busy, OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); + object_property_add(obj, PC_DIMM_RSVD_PROP, "int", pc_dimm_get_reserve= d_size, + pc_dimm_set_reserved_size, NULL, NULL, &error_abor= t); } =20 static void pc_dimm_realize(DeviceState *dev, Error **errp) diff --git a/include/hw/mem/pc-dimm.h b/include/hw/mem/pc-dimm.h index 1e483f2..99c4dfd 100644 --- a/include/hw/mem/pc-dimm.h +++ b/include/hw/mem/pc-dimm.h @@ -33,6 +33,7 @@ #define PC_DIMM_NODE_PROP "node" #define PC_DIMM_SIZE_PROP "size" #define PC_DIMM_MEMDEV_PROP "memdev" +#define PC_DIMM_RSVD_PROP "reserved-size" =20 #define PC_DIMM_UNASSIGNED_SLOT -1 =20 @@ -53,6 +54,7 @@ typedef struct PCDIMMDevice { uint64_t addr; uint32_t node; int32_t slot; + uint64_t reserved_size; HostMemoryBackend *hostmem; } PCDIMMDevice; =20 --=20 2.10.1 From nobody Sun Apr 28 00:40:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1490949817360893.7983250109545; Fri, 31 Mar 2017 01:43:37 -0700 (PDT) Received: from localhost ([::1]:39560 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cts9f-0000aB-P9 for importer@patchew.org; Fri, 31 Mar 2017 04:43:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54909) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cts8d-0008QQ-Cb for qemu-devel@nongnu.org; Fri, 31 Mar 2017 04:42:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cts8Z-000235-CJ for qemu-devel@nongnu.org; Fri, 31 Mar 2017 04:42:31 -0400 Received: from mga03.intel.com ([134.134.136.65]:21496) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cts8Z-00020h-3V for qemu-devel@nongnu.org; Fri, 31 Mar 2017 04:42:27 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Mar 2017 01:42:26 -0700 Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.159.153]) by fmsmga002.fm.intel.com with ESMTP; 31 Mar 2017 01:42:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490949747; x=1522485747; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=YqurXLSNySf0wBz3JceEkU7P+gU9FzMZ9v2DpCUVgRw=; b=wcuZLTxnQix4Kukph6+t90cBj8hUL8l3I9Zm0UKWl1r8yh+pWsXZhmFG asfhIzBEMLLAsJH5SWY6ljrYXit9Jg==; X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,251,1486454400"; d="scan'208";a="1149181040" From: Haozhong Zhang To: qemu-devel@nongnu.org Date: Fri, 31 Mar 2017 16:41:45 +0800 Message-Id: <20170331084147.32716-3-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170331084147.32716-1-haozhong.zhang@intel.com> References: <20170331084147.32716-1-haozhong.zhang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.65 Subject: [Qemu-devel] [RFC PATCH 2/4] nvdimm: add functions to initialize and perform flush on back store X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haozhong Zhang , dan.j.williams@intel.com, Xiao Guangrong , Igor Mammedov , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" fsync() is used to persist modifications to the back store. If the host NVDIMM is used as the back store, fsync() on Linux will trigger the write to the host flush hint address. Signed-off-by: Haozhong Zhang --- hw/mem/nvdimm.c | 22 ++++++++++++++++++++++ include/hw/mem/nvdimm.h | 13 +++++++++++++ 2 files changed, 35 insertions(+) diff --git a/hw/mem/nvdimm.c b/hw/mem/nvdimm.c index db896b0..484ab8b 100644 --- a/hw/mem/nvdimm.c +++ b/hw/mem/nvdimm.c @@ -78,6 +78,26 @@ static MemoryRegion *nvdimm_get_memory_region(PCDIMMDevi= ce *dimm) return &nvdimm->nvdimm_mr; } =20 +static void nvdimm_flush_init(NVDIMMDevice *nvdimm, MemoryRegion *hostmem_= mr) +{ + if (nvdimm->flush_hint_enabled) { + nvdimm->backend_fd =3D memory_region_get_fd(hostmem_mr); + } else { + nvdimm->backend_fd =3D -1; + } +} + +void nvdimm_flush(NVDIMMDevice *nvdimm) +{ + if (nvdimm->backend_fd !=3D -1) { + /* + * If the backend store is a physical NVDIMM device, fsync() + * will trigger the flush via the flush hint on the host device. + */ + fsync(nvdimm->backend_fd); + } +} + static void nvdimm_realize(PCDIMMDevice *dimm, Error **errp) { MemoryRegion *mr =3D host_memory_backend_get_memory(dimm->hostmem, err= p); @@ -105,6 +125,8 @@ static void nvdimm_realize(PCDIMMDevice *dimm, Error **= errp) memory_region_init_alias(&nvdimm->nvdimm_mr, OBJECT(dimm), "nvdimm-memory", mr, 0, pmem_size); nvdimm->nvdimm_mr.align =3D align; + + nvdimm_flush_init(nvdimm, mr); } =20 /* diff --git a/include/hw/mem/nvdimm.h b/include/hw/mem/nvdimm.h index 03e1ff9..eb71f41 100644 --- a/include/hw/mem/nvdimm.h +++ b/include/hw/mem/nvdimm.h @@ -71,6 +71,18 @@ struct NVDIMMDevice { * guest via ACPI NFIT and _FIT method if NVDIMM hotplug is supported. */ MemoryRegion nvdimm_mr; + + /* + * If true, a flush hint address structure will be built for this + * NVDIMM device. + */ + bool flush_hint_enabled; + /* + * File descriptor of the backend store, which is used in nvdimm + * flush. It's cached in NVDIMMDevice rather than being fetched + * at each request in order to accelerate the flush a little bit. + */ + int backend_fd; }; typedef struct NVDIMMDevice NVDIMMDevice; =20 @@ -132,4 +144,5 @@ void nvdimm_build_acpi(GArray *table_offsets, GArray *t= able_data, uint32_t ram_slots); void nvdimm_plug(AcpiNVDIMMState *state); void nvdimm_acpi_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev); +void nvdimm_flush(NVDIMMDevice *nvdimm); #endif --=20 2.10.1 From nobody Sun Apr 28 00:40:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1490949970220603.1351136408754; Fri, 31 Mar 2017 01:46:10 -0700 (PDT) Received: from localhost ([::1]:39575 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ctsC8-0002dD-PZ for importer@patchew.org; Fri, 31 Mar 2017 04:46:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54910) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cts8d-0008QR-Ct for qemu-devel@nongnu.org; Fri, 31 Mar 2017 04:42:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cts8b-000265-VJ for qemu-devel@nongnu.org; Fri, 31 Mar 2017 04:42:31 -0400 Received: from mga03.intel.com ([134.134.136.65]:21496) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cts8b-00020h-N5 for qemu-devel@nongnu.org; Fri, 31 Mar 2017 04:42:29 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Mar 2017 01:42:29 -0700 Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.159.153]) by fmsmga002.fm.intel.com with ESMTP; 31 Mar 2017 01:42:27 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490949749; x=1522485749; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=EN8mr9jEnqBRveGPeDkCjG0ZOvII5aODtxII8bVHI4k=; b=Xm2K7SGB/2QKmt6Laldo8RyAybHaaOKnpHaJL9w/z9mM60WAD0/BGv4A 9MSLX4cLoE7EROqhToI3WUYG6FxG/g==; X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,251,1486454400"; d="scan'208";a="1149181048" From: Haozhong Zhang To: qemu-devel@nongnu.org Date: Fri, 31 Mar 2017 16:41:46 +0800 Message-Id: <20170331084147.32716-4-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170331084147.32716-1-haozhong.zhang@intel.com> References: <20170331084147.32716-1-haozhong.zhang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.65 Subject: [Qemu-devel] [RFC PATCH 3/4] nvdimm acpi: record the cache line size in AcpiNVDIMMState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haozhong Zhang , Xiao Guangrong , "Michael S. Tsirkin" , Eduardo Habkost , Paolo Bonzini , Igor Mammedov , dan.j.williams@intel.com, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Software is allowed to write up to a cache line of data to the flush hint address (ACPI spec 6.1, Table 5-135). NVDIMM ACPI code needs this parameter to decide the address space size for flush hint addresses. Signed-off-by: Haozhong Zhang --- hw/acpi/nvdimm.c | 5 ++++- hw/i386/pc_piix.c | 2 +- hw/i386/pc_q35.c | 2 +- include/hw/mem/nvdimm.h | 5 ++++- 4 files changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c index 8e7d6ec..ea2ac3e 100644 --- a/hw/acpi/nvdimm.c +++ b/hw/acpi/nvdimm.c @@ -881,7 +881,8 @@ void nvdimm_acpi_plug_cb(HotplugHandler *hotplug_dev, D= eviceState *dev) } =20 void nvdimm_init_acpi_state(AcpiNVDIMMState *state, MemoryRegion *io, - FWCfgState *fw_cfg, Object *owner) + FWCfgState *fw_cfg, Object *owner, + unsigned int cache_line_size) { memory_region_init_io(&state->io_mr, owner, &nvdimm_dsm_ops, state, "nvdimm-acpi-io", NVDIMM_ACPI_IO_LEN); @@ -893,6 +894,8 @@ void nvdimm_init_acpi_state(AcpiNVDIMMState *state, Mem= oryRegion *io, state->dsm_mem->len); =20 nvdimm_init_fit_buffer(&state->fit_buf); + + state->cache_line_size =3D cache_line_size; } =20 #define NVDIMM_COMMON_DSM "NCAL" diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 9f102aa..81dd379 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -298,7 +298,7 @@ static void pc_init1(MachineState *machine, =20 if (pcms->acpi_nvdimm_state.is_enabled) { nvdimm_init_acpi_state(&pcms->acpi_nvdimm_state, system_io, - pcms->fw_cfg, OBJECT(pcms)); + pcms->fw_cfg, OBJECT(pcms), 64); } } =20 diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index dd792a8..19f5515 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -272,7 +272,7 @@ static void pc_q35_init(MachineState *machine) =20 if (pcms->acpi_nvdimm_state.is_enabled) { nvdimm_init_acpi_state(&pcms->acpi_nvdimm_state, system_io, - pcms->fw_cfg, OBJECT(pcms)); + pcms->fw_cfg, OBJECT(pcms), 64); } } =20 diff --git a/include/hw/mem/nvdimm.h b/include/hw/mem/nvdimm.h index eb71f41..888def6 100644 --- a/include/hw/mem/nvdimm.h +++ b/include/hw/mem/nvdimm.h @@ -134,11 +134,14 @@ struct AcpiNVDIMMState { =20 /* the IO region used by OSPM to transfer control to QEMU. */ MemoryRegion io_mr; + + unsigned int cache_line_size; }; typedef struct AcpiNVDIMMState AcpiNVDIMMState; =20 void nvdimm_init_acpi_state(AcpiNVDIMMState *state, MemoryRegion *io, - FWCfgState *fw_cfg, Object *owner); + FWCfgState *fw_cfg, Object *owner, + unsigned int cache_line_size); void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data, BIOSLinker *linker, AcpiNVDIMMState *state, uint32_t ram_slots); --=20 2.10.1 From nobody Sun Apr 28 00:40:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1490950035319509.86253973289604; Fri, 31 Mar 2017 01:47:15 -0700 (PDT) Received: from localhost ([::1]:39577 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ctsDB-0003Ax-Gz for importer@patchew.org; Fri, 31 Mar 2017 04:47:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54965) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cts8g-0008SX-8l for qemu-devel@nongnu.org; Fri, 31 Mar 2017 04:42:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cts8e-00028w-Py for qemu-devel@nongnu.org; Fri, 31 Mar 2017 04:42:34 -0400 Received: from mga03.intel.com ([134.134.136.65]:21496) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cts8e-00020h-Df for qemu-devel@nongnu.org; Fri, 31 Mar 2017 04:42:32 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Mar 2017 01:42:31 -0700 Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.159.153]) by fmsmga002.fm.intel.com with ESMTP; 31 Mar 2017 01:42:29 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490949752; x=1522485752; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=ran6SVnddXdnpvl3qFkljJcMXcsQTuOm5M8pb6eFGTM=; b=YJa7u39m6gtQwUiyf2XaZ43NkqPBM70/rxn5/MMc/PWYkZDb3gTmM4rf NUhvgwJWW4aNd0JFGekAjNWE14a8YQ==; X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,251,1486454400"; d="scan'208";a="1149181065" From: Haozhong Zhang To: qemu-devel@nongnu.org Date: Fri, 31 Mar 2017 16:41:47 +0800 Message-Id: <20170331084147.32716-5-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170331084147.32716-1-haozhong.zhang@intel.com> References: <20170331084147.32716-1-haozhong.zhang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.65 Subject: [Qemu-devel] [RFC PATCH 4/4] nvdimm acpi: build flush hint address structure if required X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haozhong Zhang , Xiao Guangrong , "Michael S. Tsirkin" , Eduardo Habkost , Paolo Bonzini , Igor Mammedov , dan.j.williams@intel.com, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add an boolean option 'flush-hint' to device 'nvdimm'. If it's on, a flush hint address structure will be constructed for each nvdimm device. Signed-off-by: Haozhong Zhang --- hw/acpi/nvdimm.c | 106 ++++++++++++++++++++++++++++++++++++++++++++= +--- hw/i386/pc.c | 5 ++- hw/mem/nvdimm.c | 26 ++++++++++++ include/hw/mem/nvdimm.h | 2 +- 4 files changed, 132 insertions(+), 7 deletions(-) diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c index ea2ac3e..a7ff0b2 100644 --- a/hw/acpi/nvdimm.c +++ b/hw/acpi/nvdimm.c @@ -32,6 +32,8 @@ #include "hw/acpi/bios-linker-loader.h" #include "hw/nvram/fw_cfg.h" #include "hw/mem/nvdimm.h" +#include "exec/address-spaces.h" +#include "qapi/error.h" =20 static int nvdimm_device_list(Object *obj, void *opaque) { @@ -168,6 +170,22 @@ struct NvdimmNfitControlRegion { typedef struct NvdimmNfitControlRegion NvdimmNfitControlRegion; =20 /* + * NVDIMM Flush Hint Address Structure + * + * It enables the data durability mechanism via ACPI. + */ +struct NvdimmNfitFlushHintAddress { + uint16_t type; + uint16_t length; + uint32_t nfit_handle; + uint16_t nr_flush_hint_addr; + uint8_t reserved[6]; +#define NR_FLUSH_HINT_ADDR 1 + uint64_t flush_hint_addr[NR_FLUSH_HINT_ADDR]; +} QEMU_PACKED; +typedef struct NvdimmNfitFlushHintAddress NvdimmNfitFlushHintAddress; + +/* * Module serial number is a unique number for each device. We use the * slot id of NVDIMM device to generate this number so that each device * associates with a different number. @@ -343,10 +361,79 @@ static void nvdimm_build_structure_dcr(GArray *struct= ures, DeviceState *dev) (DSM) in DSM Spec Rev1.*/); } =20 -static GArray *nvdimm_build_device_structure(void) +static uint64_t nvdimm_flush_hint_read(void *opaque, hwaddr addr, unsigned= size) +{ + return 0; +} + +static void nvdimm_flush_hint_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size) +{ + nvdimm_debug("Write Flush Hint: offset 0x%"HWADDR_PRIx", data 0x%"PRIx= 64"\n", + addr, data); + nvdimm_flush((NVDIMMDevice *)opaque); +} + +static const MemoryRegionOps nvdimm_flush_hint_ops =3D { + .read =3D nvdimm_flush_hint_read, + .write =3D nvdimm_flush_hint_write, +}; + +/* + * ACPI 6.0: 5.2.25.7 Flush Hint Address Structure + */ +static void nvdimm_build_structure_flush_hint(GArray *structures, + DeviceState *dev, + unsigned int cache_line_size, + Error **errp) +{ + NvdimmNfitFlushHintAddress *flush_hint; + int slot =3D object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP, N= ULL); + PCDIMMDevice *dimm =3D PC_DIMM(dev); + NVDIMMDevice *nvdimm =3D NVDIMM(dev); + uint64_t addr; + unsigned int i; + MemoryRegion *mr; + Error *local_err =3D NULL; + + if (!nvdimm->flush_hint_enabled) { + return; + } + + if (cache_line_size * NR_FLUSH_HINT_ADDR > dimm->reserved_size) { + error_setg(&local_err, + "insufficient reserved space for flush hint buffers"); + goto out; + } + + addr =3D object_property_get_int(OBJECT(dev), PC_DIMM_ADDR_PROP, NULL); + addr +=3D object_property_get_int(OBJECT(dev), PC_DIMM_SIZE_PROP, NULL= ); + + flush_hint =3D acpi_data_push(structures, sizeof(*flush_hint)); + flush_hint->type =3D cpu_to_le16(6 /* Flush Hint Address Structure */); + flush_hint->length =3D cpu_to_le16(sizeof(*flush_hint)); + flush_hint->nfit_handle =3D cpu_to_le32(nvdimm_slot_to_handle(slot)); + flush_hint->nr_flush_hint_addr =3D cpu_to_le16(NR_FLUSH_HINT_ADDR); + + for (i =3D 0; i < NR_FLUSH_HINT_ADDR; i++, addr +=3D cache_line_size) { + flush_hint->flush_hint_addr[i] =3D cpu_to_le64(addr); + + mr =3D g_new0(MemoryRegion, 1); + memory_region_init_io(mr, OBJECT(dev), &nvdimm_flush_hint_ops, nvd= imm, + "nvdimm-flush-hint", cache_line_size); + memory_region_add_subregion(get_system_memory(), addr, mr); + } + + out: + error_propagate(errp, local_err); +} + +static GArray *nvdimm_build_device_structure(AcpiNVDIMMState *state, + Error **errp) { GSList *device_list =3D nvdimm_get_device_list(); GArray *structures =3D g_array_new(false, true /* clear */, 1); + Error *local_err =3D NULL; =20 for (; device_list; device_list =3D device_list->next) { DeviceState *dev =3D device_list->data; @@ -362,9 +449,17 @@ static GArray *nvdimm_build_device_structure(void) =20 /* build NVDIMM Control Region Structure. */ nvdimm_build_structure_dcr(structures, dev); + + /* build Flush Hint Address Structure */ + nvdimm_build_structure_flush_hint(structures, dev, + state->cache_line_size, &local_e= rr); + if (local_err) { + break; + } } g_slist_free(device_list); =20 + error_propagate(errp, local_err); return structures; } =20 @@ -373,16 +468,17 @@ static void nvdimm_init_fit_buffer(NvdimmFitBuffer *f= it_buf) fit_buf->fit =3D g_array_new(false, true /* clear */, 1); } =20 -static void nvdimm_build_fit_buffer(NvdimmFitBuffer *fit_buf) +static void nvdimm_build_fit_buffer(AcpiNVDIMMState *state, Error **errp) { + NvdimmFitBuffer *fit_buf =3D &state->fit_buf; g_array_free(fit_buf->fit, true); - fit_buf->fit =3D nvdimm_build_device_structure(); + fit_buf->fit =3D nvdimm_build_device_structure(state, errp); fit_buf->dirty =3D true; } =20 -void nvdimm_plug(AcpiNVDIMMState *state) +void nvdimm_plug(AcpiNVDIMMState *state, Error **errp) { - nvdimm_build_fit_buffer(&state->fit_buf); + nvdimm_build_fit_buffer(state, errp); } =20 static void nvdimm_build_nfit(AcpiNVDIMMState *state, GArray *table_offset= s, diff --git a/hw/i386/pc.c b/hw/i386/pc.c index d24388e..da4a5d7 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1718,7 +1718,10 @@ static void pc_dimm_plug(HotplugHandler *hotplug_dev, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); goto out; } - nvdimm_plug(&pcms->acpi_nvdimm_state); + nvdimm_plug(&pcms->acpi_nvdimm_state, &local_err); + if (local_err) { + goto out; + } } =20 hhc =3D HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); diff --git a/hw/mem/nvdimm.c b/hw/mem/nvdimm.c index 484ab8b..a26908b 100644 --- a/hw/mem/nvdimm.c +++ b/hw/mem/nvdimm.c @@ -64,11 +64,37 @@ out: error_propagate(errp, local_err); } =20 +static bool nvdimm_get_flush_hint(Object *obj, Error **errp) +{ + NVDIMMDevice *nvdimm =3D NVDIMM(obj); + + return nvdimm->flush_hint_enabled; +} + +static void nvdimm_set_flush_hint(Object *obj, bool val, Error **errp) +{ + NVDIMMDevice *nvdimm =3D NVDIMM(obj); + Error *local_err =3D NULL; + + if (nvdimm->flush_hint_enabled) { + error_setg(&local_err, "cannot change property value"); + goto out; + } + + nvdimm->flush_hint_enabled =3D val; + + out: + error_propagate(errp, local_err); +} + static void nvdimm_init(Object *obj) { object_property_add(obj, "label-size", "int", nvdimm_get_label_size, nvdimm_set_label_size, NULL, NULL, NULL); + object_property_add_bool(obj, "flush-hint", + nvdimm_get_flush_hint, nvdimm_set_flush_hint, + NULL); } =20 static MemoryRegion *nvdimm_get_memory_region(PCDIMMDevice *dimm) diff --git a/include/hw/mem/nvdimm.h b/include/hw/mem/nvdimm.h index 888def6..726f4d9 100644 --- a/include/hw/mem/nvdimm.h +++ b/include/hw/mem/nvdimm.h @@ -145,7 +145,7 @@ void nvdimm_init_acpi_state(AcpiNVDIMMState *state, Mem= oryRegion *io, void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data, BIOSLinker *linker, AcpiNVDIMMState *state, uint32_t ram_slots); -void nvdimm_plug(AcpiNVDIMMState *state); +void nvdimm_plug(AcpiNVDIMMState *state, Error **errp); void nvdimm_acpi_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev); void nvdimm_flush(NVDIMMDevice *nvdimm); #endif --=20 2.10.1