From nobody Sun Oct 5 20:55:06 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1489435134517673.2451532944601; Mon, 13 Mar 2017 12:58:54 -0700 (PDT) Received: from localhost ([::1]:54108 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cnW7J-0002EM-BT for importer@patchew.org; Mon, 13 Mar 2017 15:58:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42764) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cnW4T-0000aR-Hw for qemu-devel@nongnu.org; Mon, 13 Mar 2017 15:56:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cnW4S-0002LY-GR for qemu-devel@nongnu.org; Mon, 13 Mar 2017 15:55:57 -0400 Received: from mx1.redhat.com ([209.132.183.28]:38582) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cnW4S-0002LC-82 for qemu-devel@nongnu.org; Mon, 13 Mar 2017 15:55:56 -0400 Received: from smtp.corp.redhat.com (int-mx16.intmail.prod.int.phx2.redhat.com [10.5.11.28]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 2B5C581220; Mon, 13 Mar 2017 19:55:56 +0000 (UTC) Received: from red.redhat.com (unknown [10.10.121.21]) by smtp.corp.redhat.com (Postfix) with ESMTP id 11B652D5C9; Mon, 13 Mar 2017 19:55:54 +0000 (UTC) From: Eric Blake To: qemu-devel@nongnu.org Date: Mon, 13 Mar 2017 14:55:20 -0500 Message-Id: <20170313195547.21466-4-eblake@redhat.com> In-Reply-To: <20170313195547.21466-1-eblake@redhat.com> References: <20170313195547.21466-1-eblake@redhat.com> X-Scanned-By: MIMEDefang 2.74 on 10.5.11.28 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Mon, 13 Mar 2017 19:55:56 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 03/30] trace: Avoid abuse of amdvi_mmio_read X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , "Michael S. Tsirkin" , Eduardo Habkost , stefanha@redhat.com, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" hw/i386/trace-events has an amdvi_mmio_read trace that is used for both normal reads (listing the register name, address, size, and offset) and for an error case (abusing the register name to show an error message, the address to show the maximum value supported, then shoehorning address and size into the size and offset parameters). The change from a wide address to a narrower size parameter could truncate a (rather-large) bogus read attempt, so it's better to create a separate dedicated trace with correct types, rather than abusing the trace mechanism. Broken since its introduction in commit d29a09c. Signed-off-by: Eric Blake --- hw/i386/amd_iommu.c | 3 +-- hw/i386/trace-events | 1 + 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index e0732cc..f86a40a 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -572,8 +572,7 @@ static uint64_t amdvi_mmio_read(void *opaque, hwaddr ad= dr, unsigned size) uint64_t val =3D -1; if (addr + size > AMDVI_MMIO_SIZE) { - trace_amdvi_mmio_read("error: addr outside region: max ", - (uint64_t)AMDVI_MMIO_SIZE, addr, size); + trace_amdvi_mmio_read_invalid(AMDVI_MMIO_SIZE, addr, size); return (uint64_t)-1; } diff --git a/hw/i386/trace-events b/hw/i386/trace-events index 88ad5e4..a213bfd 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -37,6 +37,7 @@ amdvi_cache_update(uint16_t domid, uint8_t bus, uint8_t s= lot, uint8_t func, uint amdvi_completion_wait_fail(uint64_t addr) "error: fail to write at address= 0x%"PRIx64 amdvi_mmio_write(const char *reg, uint64_t addr, unsigned size, uint64_t v= al, uint64_t offset) "%s write addr 0x%"PRIx64", size %u, val 0x%"PRIx64", = offset 0x%"PRIx64 amdvi_mmio_read(const char *reg, uint64_t addr, unsigned size, uint64_t of= fset) "%s read addr 0x%"PRIx64", size %u offset 0x%"PRIx64 +amdvi_mmio_read_invalid(int max, hwaddr addr, unsigned size) "error: addr = outside region (max 0x%x): read addr 0x%" HWADDR_PRIx ", size %u" amdvi_command_error(uint64_t status) "error: Executing commands with comma= nd buffer disabled 0x%"PRIx64 amdvi_command_read_fail(uint64_t addr, uint32_t head) "error: fail to acce= ss memory at 0x%"PRIx64" + 0x%"PRIx32 amdvi_command_exec(uint32_t head, uint32_t tail, uint64_t buf) "command bu= ffer head at 0x%"PRIx32" command buffer tail at 0x%"PRIx32" command buffer = base at 0x%"PRIx64 --=20 2.9.3