From nobody Mon May 6 00:41:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488886718084290.81207118245584; Tue, 7 Mar 2017 03:38:38 -0800 (PST) Received: from localhost ([::1]:49346 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1clDRp-0006Wy-W0 for importer@patchew.org; Tue, 07 Mar 2017 06:38:34 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59148) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1clDR2-0006Wq-4n for qemu-devel@nongnu.org; Tue, 07 Mar 2017 06:37:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1clDQz-0000Od-1u for qemu-devel@nongnu.org; Tue, 07 Mar 2017 06:37:44 -0500 Received: from mx1.redhat.com ([209.132.183.28]:53156) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1clDQy-0000O9-Ow for qemu-devel@nongnu.org; Tue, 07 Mar 2017 06:37:40 -0500 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 68E5D800; Tue, 7 Mar 2017 11:37:40 +0000 (UTC) Received: from donizetti.redhat.com (ovpn-117-228.ams2.redhat.com [10.36.117.228]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id v27Bbb3w006776; Tue, 7 Mar 2017 06:37:37 -0500 From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 7 Mar 2017 12:37:36 +0100 Message-Id: <20170307113736.13864-1-pbonzini@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.27 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Tue, 07 Mar 2017 11:37:40 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH] target-i386: defer VMEXIT to do_interrupt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, alexander.boettcher@genode-labs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Paths through the softmmu code during code generation now need to be audited to check for double locking of tb_lock. In particular, VMEXIT can take tb_= lock through cpu_vmexit -> cpu_x86_update_cr4 -> tlb_flush. To avoid this, split VMEXIT delivery in two parts, similar to what is done = with exceptions. cpu_vmexit only records the VMEXIT exit code and information, = and cc->do_interrupt can then deliver it when it is safe to take the lock. Reported-by: Alexander Boettcher Suggested-by: Richard Henderson Tested-by: Alexander Boettcher Signed-off-by: Paolo Bonzini Reviewed-by: Alex Benn=C3=A9e --- target/i386/cpu.h | 2 ++ target/i386/seg_helper.c | 20 +++++++++++--------- target/i386/svm_helper.c | 22 +++++++++++++--------- 3 files changed, 26 insertions(+), 18 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ac2ad6d..40a6ff7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -694,6 +694,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; =20 #define EXCP_SYSCALL 0x100 /* only happens in user only emulation for syscall instruction */ +#define EXCP_VMEXIT 0x100 =20 /* i386-specific interrupt pending bits. */ #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 @@ -1629,6 +1630,7 @@ void cpu_svm_check_intercept_param(CPUX86State *env1,= uint32_t type, uint64_t param, uintptr_t retaddr); void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_= 1, uintptr_t retaddr); +void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); =20 /* seg_helper.c */ void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); diff --git a/target/i386/seg_helper.c b/target/i386/seg_helper.c index 5c845dc..0374031 100644 --- a/target/i386/seg_helper.c +++ b/target/i386/seg_helper.c @@ -1297,15 +1297,17 @@ void x86_cpu_do_interrupt(CPUState *cs) /* successfully delivered */ env->old_exception =3D -1; #else - /* simulate a real cpu exception. On i386, it can - trigger new exceptions, but we do not handle - double or triple faults yet. */ - do_interrupt_all(cpu, cs->exception_index, - env->exception_is_int, - env->error_code, - env->exception_next_eip, 0); - /* successfully delivered */ - env->old_exception =3D -1; + if (cs->exception_index >=3D EXCP_VMEXIT) { + assert(env->old_exception =3D=3D -1); + do_vmexit(env, cs->exception_index - EXCP_VMEXIT, env->error_code); + } else { + do_interrupt_all(cpu, cs->exception_index, + env->exception_is_int, + env->error_code, + env->exception_next_eip, 0); + /* successfully delivered */ + env->old_exception =3D -1; + } #endif } =20 diff --git a/target/i386/svm_helper.c b/target/i386/svm_helper.c index 78d8df4..59e8b50 100644 --- a/target/i386/svm_helper.c +++ b/target/i386/svm_helper.c @@ -580,12 +580,10 @@ void helper_svm_check_io(CPUX86State *env, uint32_t p= ort, uint32_t param, } } =20 -/* Note: currently only 32 bits of exit_code are used */ void cpu_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1, uintptr_t retaddr) { CPUState *cs =3D CPU(x86_env_get_cpu(env)); - uint32_t int_ctl; =20 if (retaddr) { cpu_restore_state(cs, retaddr); @@ -598,6 +596,19 @@ void cpu_vmexit(CPUX86State *env, uint32_t exit_code, = uint64_t exit_info_1, control.exit_info_2)), env->eip); =20 + cs->exception_index =3D EXCP_VMEXIT + exit_code; + env->error_code =3D exit_info_1; + + /* remove any pending exception */ + env->old_exception =3D -1; + cpu_loop_exit(cs); +} + +void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1) +{ + CPUState *cs =3D CPU(x86_env_get_cpu(env)); + uint32_t int_ctl; + if (env->hflags & HF_INHIBIT_IRQ_MASK) { x86_stl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.int_state), @@ -759,13 +770,6 @@ void cpu_vmexit(CPUX86State *env, uint32_t exit_code, = uint64_t exit_info_1, /* If the host's rIP reloaded by #VMEXIT is outside the limit of the host's code segment or non-canonical (in the case of long mode), a #GP fault is delivered inside the host. */ - - /* remove any pending exception */ - cs->exception_index =3D -1; - env->error_code =3D 0; - env->old_exception =3D -1; - - cpu_loop_exit(cs); } =20 #endif --=20 2.9.3